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公开(公告)号：US20180373902A1
公开(公告)日：2018-12-27
申请号：US16063892
申请日：2016-01-21
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Ben Feinberg
Abstract: A circuit includes an engine to compute analog multiplication results between vectors of a sub-matrix, An analog to digital converter (ADC) generates a digital value for the analog multiplication results computed by the engine. A shifter shifts the digital value of analog multiplication results a predetermined number of bits to generate a shifted result. An adder adds the shifted result to the digital value of a second multiplication result to generate a combined multiplication result.
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公开(公告)号：US20180004708A1
公开(公告)日：2018-01-04
申请号：US15201040
申请日：2016-07-01
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Ben Feinberg , Ali Shafiee-Ardestani
Abstract: Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.
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公开(公告)号：US10754582B2
公开(公告)日：2020-08-25
申请号：US16073534
申请日：2016-03-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Ali Shafiee Ardestani , Ben Feinberg
Abstract: In an example, a method includes receiving input data and dividing the input data into a plurality of data portions, wherein the size of each data portion is based on a significance level. The input data may be assigned to at least one resistive memory array. Assigning the input data to at least one resistive memory array may comprises at least one of (i) assigning at least one data portion of the input data to be represented by a resistive memory array representing a number of bits, wherein the number of bits represented within the resistive memory array is based on the size of the at least one data portion; and (ii) processing each data portion of the input data with at least one resistive memory array.
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公开(公告)号：US09910827B2
公开(公告)日：2018-03-06
申请号：US15201040
申请日：2016-07-01
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Naveen Muralimanohar , Ben Feinberg , Ali Shafiee-Ardestani
Abstract: Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.
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