公开(公告)号：US20060197850A1

公开(公告)日：2006-09-07

申请号：US11239009

申请日：2005-09-30

申请人： Hiroki Goko ,  Kenichi Shindate ,  Shinya Hirasaki ,  Junichi Tamura

发明人： Hiroki Goko ,  Kenichi Shindate ,  Shinya Hirasaki ,  Junichi Tamura

IPC分类号： H04N5/76

CPC分类号： H04N5/2353 ,  H04N5/23241 ,  H04N5/23293 ,  H04N5/772

摘要： The present invention provides a camera data transfer system comprising an imaging means for generating image data and outputting the same, and a camera interface means including a first holding means for holding one frame-preceding image data, a second holding means for holding the present image data, a comparing means for comparing the contents of the first and second holding means, and a bus interface means for controlling the input/output of data to and from a bus. In the camera data transfer system, the data is transferred to a frame memory of a display means connected to the bus through the bus interface means to cause the frame memory to display the data thereon. Further, when the data held in the first holding means and the data held in the second holding means are found not to coincide with each other as the result of comparison by the comparing means, only a place corresponding to the inconsistent data is transferred to the frame memory of the display means, and the data at the corresponding place of the first holding means is rewritten.

摘要翻译： 本发明提供一种相机数据传送系统，包括用于产生图像数据和输出图像数据的成像装置，以及包括用于保持一帧前一图像数据的第一保持装置的相机接口装置，用于保持当前图像的第二保持装置 数据，用于比较第一和第二保持装置的内容的比较装置，以及用于控制与总线的数据的输入/输出的总线接口装置。 在相机数据传送系统中，通过总线接口装置将数据传送到连接到总线的显示装置的帧存储器，以使帧存储器在其上显示数据。 作为比较装置的比较结果，当保持在第一保持装置中的数据和保持在第二保持装置中的数据被发现彼此不一致时，只有与不一致的数据相对应的地方被传送到 显示装置的帧存储器，并且重写第一保持装置的相应位置处的数据。

公开(公告)号：US20050149798A1

公开(公告)日：2005-07-07

申请号：US10999976

申请日：2004-12-01

申请人： Kohtaro Inuzuka ,  Junichi Tamura ,  Hiroki Goko ,  Osamu Endoh

发明人： Kohtaro Inuzuka ,  Junichi Tamura ,  Hiroki Goko ,  Osamu Endoh

IPC分类号： G01R31/28 ,  G06F11/22 ,  H01L21/822 ,  H01L27/04

CPC分类号： G01R31/318536

摘要： The present invention provides a LSI being capable of testing a signal path between two circuit blocks by a scan isolation test. A scan isolation circuit 30-1 includes a first selector 31 alternating a held signal S33 or a signal SA from circuit block 10A and outputting the alternated signal thereof as signals 31, and a second selector 32 selecting the signal S31 or one signal from the signal SAm from outside or the previous-stage signal S33. Further, the held signal S33 held in the FF 33 thereof is supplied to the selector 31 and the next-stage scan isolation circuit 30-2, connecting the FF 33 to the output terminal. During the test therein, since the signal SA is held through the selectors 31 and 32, the signal path between the circuit blocks 10A and 10B can be conducted.

摘要翻译： 本发明提供一种能够通过扫描隔离测试来测试两个电路块之间的信号路径的LSI。 扫描隔离电路30-1包括第一选择器31，交替保持信号S33或来自电路块10A的信号SA，并将其交替信号作为信号31输出，第二选择器32选择信号S31或一个信号 来自外部的信号SAm或前一级信号S 33。 此外，保持在其FF33中的保持信号S33被提供给选择器31和下一级扫描隔离电路30-2，将FF 33连接到输出端。 在其中的测试中，由于信号SA通过选择器31和32保持，所以可以进行电路块10A和10B之间的信号路径。

公开(公告)号：US20050120318A1

公开(公告)日：2005-06-02

申请号：US10813031

申请日：2004-03-31

申请人： Hiroki Goko ,  Junichi Tamura

发明人： Hiroki Goko ,  Junichi Tamura

IPC分类号： G06F17/50 ,  G06F9/45 ,  H01L21/82

CPC分类号： G06F17/5045

摘要： The present invention provides an apparatus for designing a semiconductor integrated circuit, which is capable of satisfying timing constraints without providing BFBs, and improving a convergent property at optimization, and a design method therefor. An LSI automatic design simulator (10) determines the number of clocks employed in a clock generating functional part (30) and delays in respective clocks, allocates the clocks set as clock systems, and verifies constraint conditions with respect to design, based on the respective clocks. A tree determining functional part (32) adjusts skews of the respective clocks through the use of the produced cock systems, makes delay adjustments to the clocks, verifies a layout adjustment, and fetches therein data supplied thereto without timing constraint violation, thereby making it possible to further enhance a convergent property that satisfies all of timing constraints.

摘要翻译： 本发明提供一种用于设计半导体集成电路的装置，其能够在不提供BFB的情况下满足定时约束，并且在优化时提高收敛特性及其设计方法。 LSI自动设计模拟器（10）确定在时钟产生功能部件（30）中采用的时钟数量和各个时钟的延迟，分配设置为时钟系统的时钟，并基于相应的设计来验证关于设计的约束条件 时钟。 树确定功能部件（32）通过使用所产生的旋塞系统来调整各个时钟的偏移量，对时钟进行延迟调整，验证布局调整，并且在其中取出提供给其的数据，而没有定时约束违反，从而使其成为可能 以进一步增强满足所有时序约束的收敛性质。

公开(公告)号：US07065686B2

公开(公告)日：2006-06-20

申请号：US10173826

申请日：2002-06-19

申请人： Nobuyuki Endo ,  Yuji Fujiki ,  Hiroki Goko ,  Fumihiro Wajima ,  Junichi Tamura ,  Ali Elhadri

发明人： Nobuyuki Endo ,  Yuji Fujiki ,  Hiroki Goko ,  Fumihiro Wajima ,  Junichi Tamura ,  Ali Elhadri

IPC分类号： G11C29/00

CPC分类号： G11C29/12015 ,  G11C8/16 ,  G11C29/14

摘要： A dual port RAM includes an any-time readable/writable memory block in which an access can be made to the same storage area from independent first and second ports. In addition, the RAM includes a first test circuit for performing a test to the storage area of the memory block via the first port on the basis of a first clock signal, and a second test circuit for performing a test to the storage area of the memory block via the second port on the basis of a second clock signal. A control circuit of the RAM causes the first and second test circuits to test the memory block in an alternating manner.

公开(公告)号：US06981109B2

公开(公告)日：2005-12-27

申请号：US10252402

申请日：2002-09-24

申请人： Hiroki Goko ,  Fumihiro Wajima ,  Yuji Fujiki ,  Junichi Tamura ,  Ali Elhadri ,  Nobuyuki Endo

发明人： Hiroki Goko ,  Fumihiro Wajima ,  Yuji Fujiki ,  Junichi Tamura ,  Ali Elhadri ,  Nobuyuki Endo

IPC分类号： G06F11/00 ,  G06F12/00 ,  G06F12/14

CPC分类号： G06F9/3802

摘要： A digital signal processor includes a programmable memory, a processor and an access controller. The programmable memory has blocks each of which is capable of reading and writing an instruction of a program. The processor sequentially executes the instruction stored in the programmable memory. The access controller sequentially stores the instruction of the program in the blocks of the programmable memory on the basis of an address indicating a location of the respective blocks where the instruction is stored. The access controller controls an access of the processor to the respective blocks.

摘要翻译： 数字信号处理器包括可编程存储器，处理器和存取控制器。 可编程存储器具有能够读取和写入程序的指令的块。 处理器顺序地执行存储在可编程存储器中的指令。 访问控制器基于指示存储指令的相应块的位置的地址，顺序地将程序的指令存储在可编程存储器的块中。 访问控制器控制处理器对相应块的访问。

公开(公告)号：US06601198B1

公开(公告)日：2003-07-29

申请号：US09560885

申请日：2000-04-28

申请人： Hiroki Goko

发明人： Hiroki Goko

IPC分类号： G11C2900

CPC分类号： G01R31/2891 ,  G01R31/3177 ,  G01R31/318502

摘要： A semiconductor integrated circuit includes logic circuits, each of which receives an input signal and generates an output signal having bits, and a selector which is coupled to the logic circuits and selectively transfers either one of the output signals output from the logic circuits in response to a selection signal. The semiconductor integrated circuit also includes a comparator which compares the output signals output from the logic circuits with an expected value signal and outputs a result of the comparison, and output terminals. The semiconductor integrated circuit also includes an output buffer which is coupled between the selector and the output terminals, and which controls transferring the output signal transferred from the selector to the output terminals in response to the result of the comparison.

摘要翻译： 半导体集成电路包括逻辑电路，每个逻辑电路接收输入信号并产生具有位的输出信号，以及选择器，其耦合到逻辑电路，并响应于逻辑电路选择性地传送从逻辑电路输出的任一个输出信号 选择信号。 半导体集成电路还包括比较器，其比较来自逻辑电路的输出信号与预期值信号，并输出比较结果和输出端子。 半导体集成电路还包括输出缓冲器，其耦合在选择器和输出端子之间，并且响应于比较的结果控制将从选择器传送的输出信号传送到输出端子。

公开(公告)号：US07350037B2

公开(公告)日：2008-03-25

申请号：US10771339

申请日：2004-02-05

申请人： Fumihiro Wajima ,  Hiroki Goko

发明人： Fumihiro Wajima ,  Hiroki Goko

IPC分类号： G06F12/00

CPC分类号： G06F9/44521

摘要： A signal processing device has a program memory for storing program code transferred from an external source under the control of an access control unit having an address counter. The transferred program code is executed by a computational unit having a program counter. The access control unit controls the transfer of the program code according to the values of both the address counter and the program counter, thereby enabling the computational unit to start executing the program code before the entire program has been transferred. Program initialization can therefore be completed quickly, and the program can promptly begin producing audible or visible results.

摘要翻译： 信号处理装置具有用于存储在具有地址计数器的访问控制单元的控制下从外部源传送的程序代码的程序存储器。 所传输的程序代码由具有程序计数器的计算单元执行。 访问控制单元根据地址计数器和程序计数器的值控制程序代码的传送，从而使计算单元能够在整个程序被传送之前开始执行程序代码。 因此，程序初始化可以快速完成，程序可以立即开始产生可听见或可见的结果。

公开(公告)号：US20070288724A1

公开(公告)日：2007-12-13

申请号：US11730001

申请日：2007-03-29

申请人： Hiroki Goko ,  Kenichi Morioka

发明人： Hiroki Goko ,  Kenichi Morioka

IPC分类号： G06F9/30 ,  G06F15/00 ,  G06F9/40

CPC分类号： G06F9/3867 ,  G06F9/30079 ,  G06F9/3869

摘要： Halting clocks of pipeline registers 28-31 and data memory 26, etc., and holding input data of each of FE, DC, MEM, WB stages, during when a nop is sent to each of pipelines, by a first process for outputting a nop signal S41 of logic level “H” when the nop is detected by a nop detecting circuit 41, a second process for sending the detected nop signal to each of the pipelines by F/Fs 46-48 placed between each of the pipelines, and a third process for halting clocks by clock control circuits 42-45 placed in each of the pipelines when the nop signal is sent to each of the pipelines.

摘要翻译： 在nop被发送到每个管线期间，通过用于输出一个第一进程的时间，将流水线寄存器28-31和数据存储器26等的时钟暂停并保持FE，DC，MEM，WB级中的每一个的输入数据 由nop检测电路41检测到nop时的逻辑电平“H”的nop信号S 41，用于通过设置在每个管线之间的F / F 46-48将检测到的nop信号发送到每个管线的第二处理， 以及当nop信号被发送到每个管道时，通过时钟控制电路42-45暂停时钟的第三处理，其被放置在每个管道中。

公开(公告)号：US20050289492A1

公开(公告)日：2005-12-29

申请号：US10993490

申请日：2004-11-22

申请人： Hiroki Goko

发明人： Hiroki Goko

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5031

摘要： An LSI designing method using one or more functional blocks each containing two or more flip flops, includes the following: preparing a timing model which can be used under a first mode and a second mode; performing functional design of some functional elements each of which includes one or more functional blocks; carrying out logic composition with respect to the functional elements decided by the functional design using the timing model of the functional blocks under the first mode; performing a first timing analysis with respect to the functional elements on which logic composition was carried out using the timing model under the first mode; performing layout based on the result of the logic composition and the first timing analysis; and performing a second timing analysis after the layout using the timing model under the second mode.

摘要翻译： 使用包含两个或更多个触发器的一个或多个功能块的LSI设计方法包括以下：准备可在第一模式和第二模式下使用的定时模型; 执行一些功能元件的功能设计，每个功能元件包括一个或多个功能块; 使用第一模式下的功能块的定时模型来执行关于由功能设计决定的功能元件的逻辑组成; 使用第一模式下的定时模型，对执行逻辑组合的功能元件执行第一定时分析; 基于逻辑组成和第一时序分析的结果执行布局; 以及在第二模式下使用定时模型在布局之后执行第二定时分析。

公开(公告)号：US07284217B2

公开(公告)日：2007-10-16

申请号：US10993490

申请日：2004-11-22

申请人： Hiroki Goko

发明人： Hiroki Goko

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An LSI designing method using one or more functional blocks each containing two or more flip flops, includes the following: preparing a timing model which can be used under a first mode and a second mode; performing functional design of some functional elements each of which includes one or more functional blocks; carrying out logic composition with respect to the functional elements decided by the functional design using the timing model of the functional blocks under the first mode; performing a first timing analysis with respect to the functional elements on which logic composition was carried out using the timing model under the first mode; performing layout based on the result of the logic composition and the first timing analysis; and performing a second timing analysis after the layout using the timing model under the second mode.

摘要翻译： 使用包含两个或更多个触发器的一个或多个功能块的LSI设计方法包括以下：准备可在第一模式和第二模式下使用的定时模型; 执行一些功能元件的功能设计，每个功能元件包括一个或多个功能块; 使用第一模式下的功能块的定时模型来执行关于由功能设计决定的功能元件的逻辑组成; 使用第一模式下的定时模型，对执行逻辑组合的功能元件执行第一定时分析; 基于逻辑组成和第一时序分析的结果执行布局; 以及在第二模式下使用定时模型在布局之后执行第二定时分析。