公开(公告)号：US20210043245A1

公开(公告)日：2021-02-11

申请号：US17080242

申请日：2020-10-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Bingwu Ji ,  Tanfu Zhao ,  Yunming Zhou ,  Min Fan ,  Zhiyan Li ,  Yunpeng Wang

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/408 ,  G11C11/4074 ,  G11C7/10

Abstract: A memory and a signal processing method are provided. The memory includes a latch circuit, a decoding circuit, a storage array, a read circuit, and a write circuit. The storage array includes M rows and N columns of bitcells. The latch circuit is configured to receive a first address and a second address. The decoding circuit is configured to: determine a first bitcell based on the first address, and determine a second bitcell based on the second address. The write circuit is configured to: receive data, and write the data into the first bitcell through a first port of the first bitcell. The read circuit is configured to read, through the first port of the first bitcell, data stored in the first bitcell; and is further configured to read, through a second port of the second bitcell, data stored in the second bitcell. Implementing this application can implement 1R1RW.

公开(公告)号：US20210295906A1

公开(公告)日：2021-09-23

申请号：US17226614

申请日：2021-04-09

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sijie Chi ,  Bingwu Ji ,  Tanfu Zhao ,  Yunming Zhou

IPC: G11C11/419 ,  G11C11/54 ,  G06N3/063

Abstract: A storage unit includes a latch, and the latch provides a first storage bit. The storage unit further includes a first MOS transistor. A gate of the first MOS transistor is connected to the first storage bit, a source of the first MOS transistor is connected to a first read line, and a drain of the first MOS transistor is connected to a second read line. In a first state, the first read line is a read word line, and the second read line is a read bit line; or in a second state, the second read line is a read word line, and the first read line is a read bit line.

公开(公告)号：US11004502B2

公开(公告)日：2021-05-11

申请号：US16807594

申请日：2020-03-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sijie Chi ,  Bingwu Ji ,  Tanfu Zhao ,  Yunming Zhou

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: A storage unit and a static random access memory (SRAM), where storage unit includes a latch, and the latch provides a first storage bit. The storage unit further includes a first metal-oxide-semiconductor (MOS) transistor. A gate of the first MOS transistor is coupled to the first storage bit, a source of the first MOS transistor is coupled to a first read line, and a drain of the first MOS transistor is coupled to a second read line. In a first state, the first read line is a read word line, and the second read line is a read bit line, or in a second state, the second read line is a read word line, and the first read line is a read bit line. The storage unit according to embodiments of the present invention can implement an exchange between a read word line and a read bit line.

公开(公告)号：US20140043889A1

公开(公告)日：2014-02-13

申请号：US14057863

申请日：2013-10-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Bingwu Ji ,  Yunming Zhou ,  Tanfu Zhao ,  Wei Lin

IPC: G11C11/413

CPC classification number: G11C11/413 ,  G11C8/18 ,  G11C11/41 ,  G11C11/418 ,  G11C11/419

Abstract: A timing processing method and a circuit for a synchronous SRAM are provided. The method includes: directly inputting an address signal to a wordline decoder for logic decoding; generating various signals by setting various devices in terms of timing; and performing sensitive amplification on data that is input by a memory cell array and is selected by a bitline, and then outputting the data, that is, generating a data output signal. The circuit for a synchronous SRAM includes: a wordline decoder, a timing generator, a wordline controller, a wordline pulse width generator, a memory cell array, and a sense amplifier.

Abstract translation: 提供了一种定时处理方法和用于同步SRAM的电路。 该方法包括：将地址信号直接输入到字线解码器进行逻辑解码; 通过在定时方面设定各种装置来产生各种信号; 对由存储单元阵列输入的数据执行敏感放大，并由位线选择，然后输出数据，即产生数据输出信号。 用于同步SRAM的电路包括：字线解码器，定时发生器，字线控制器，字线脉冲宽度发生器，存储单元阵列和读出放大器。

公开(公告)号：US11475943B2

公开(公告)日：2022-10-18

申请号：US17226614

申请日：2021-04-09

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sijie Chi ,  Bingwu Ji ,  Tanfu Zhao ,  Yunming Zhou

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: A storage unit includes a latch, and the latch provides a first storage bit. The storage unit further includes a first MOS transistor. A gate of the first MOS transistor is connected to the first storage bit, a source of the first MOS transistor is connected to a first read line, and a drain of the first MOS transistor is connected to a second read line. In a first state, the first read line is a read word line, and the second read line is a read bit line; or in a second state, the second read line is a read word line, and the first read line is a read bit line.

公开(公告)号：US08988932B2

公开(公告)日：2015-03-24

申请号：US14057863

申请日：2013-10-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Bingwu Ji ,  Yunming Zhou ,  Tanfu Zhao ,  Wei Lin

IPC: G11C11/00 ,  G11C11/413 ,  G11C11/419 ,  G11C8/18 ,  G11C11/418 ,  G11C11/41

CPC classification number: G11C11/413 ,  G11C8/18 ,  G11C11/41 ,  G11C11/418 ,  G11C11/419

Abstract: A timing processing method and a circuit for a synchronous SRAM are provided. The method includes: directly inputting an address signal to a wordline decoder for logic decoding; generating various signals by setting various devices in terms of timing; and performing sensitive amplification on data that is input by a memory cell array and is selected by a bitline, and then outputting the data, that is, generating a data output signal. The circuit for a synchronous SRAM includes: a wordline decoder, a timing generator, a wordline controller, a wordline pulse width generator, a memory cell array, and a sense amplifier.

Abstract translation: 提供了一种定时处理方法和用于同步SRAM的电路。 该方法包括：将地址信号直接输入到字线解码器进行逻辑解码; 通过在定时方面设定各种装置来产生各种信号; 对由存储单元阵列输入的数据执行敏感放大，并由位线选择，然后输出数据，即产生数据输出信号。 用于同步SRAM的电路包括：字线解码器，定时发生器，字线控制器，字线脉冲宽度发生器，存储单元阵列和读出放大器。

公开(公告)号：US12087380B2

公开(公告)日：2024-09-10

申请号：US17894233

申请日：2022-08-24

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Bingwu Ji ,  Xingyi Wang ,  Yunming Zhou ,  Tanfu Zhao ,  Chuhua Hu

IPC: G11C29/52 ,  G11C5/14 ,  G11C29/02

CPC classification number: G11C29/025 ,  G11C5/14 ,  G11C29/52

Abstract: This application provides a memory, a chip, and a method for storing repair information of the memory. The memory includes a repair circuit that is configured to receive a first signal from a processor and determine to be powered by a first power supply or a second power supply based on a status of the first signal, to store repair information. The repair information is information of the failed bit cells in the memory. The first power supply is zero or in a high impedance state when a system is powered off, and the second power supply is not zero when the system is powered off. The memory further comprises a processing circuit configured to perform communication between the memory and the processor based on the repair information. Therefore, the repair information of the memory can be stored even during power loss.

公开(公告)号：US11276458B2

公开(公告)日：2022-03-15

申请号：US17080242

申请日：2020-10-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Bingwu Ji ,  Tanfu Zhao ,  Yunming Zhou ,  Min Fan ,  Zhiyan Li ,  Yunpeng Wang

IPC: G11C8/00 ,  G11C11/4091 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4094

Abstract: A memory and a signal processing method are provided. The memory includes a latch circuit, a decoding circuit, a storage array, a read circuit, and a write circuit. The storage array includes M rows and N columns of bitcells. The latch circuit is configured to receive a first address and a second address. The decoding circuit is configured to: determine a first bitcell based on the first address, and determine a second bitcell based on the second address. The write circuit is configured to: receive data, and write the data into the first bitcell through a first port of the first bitcell. The read circuit is configured to read, through the first port of the first bitcell, data stored in the first bitcell; and is further configured to read, through a second port of the second bitcell, data stored in the second bitcell. Implementing this application can implement 1R1RW.