公开(公告)号：US10141250B2

公开(公告)日：2018-11-27

申请号：US14980484

申请日：2015-12-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yuchen Xin ,  Nan Zhao ,  Chen Wang

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H05K1/18

Abstract: A chip includes a substrate and a die that are wrapped together by means of a packaging process. Multiple substrate cables corresponding to attachment points are laid out in the substrate. Solder joints in a solder joint matrix at a bottom of the substrate include a first solder joint group and a second solder joint group that are arranged along two parallel lines. Substrate cables connected to solder joints in the first solder joint group have an equal length. Substrate cables connected to solder joints in the second solder joint group have an equal length.

公开(公告)号：US20160197051A1

公开(公告)日：2016-07-07

申请号：US14980484

申请日：2015-12-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yuchen Xin ,  Nan Zhao ,  Chen Wang

IPC: H01L23/00 ,  H01L23/498 ,  H05K1/18

CPC classification number: H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2924/15311 ,  H05K1/181 ,  H01L2924/014

Abstract: A chip includes a substrate and a die that are wrapped together by means of a packaging process. Multiple substrate cables corresponding to attachment points are laid out in the substrate. Solder joints in a solder joint matrix at a bottom of the substrate include a first solder joint group and a second solder joint group that are arranged along two parallel lines. Substrate cables connected to solder joints in the first solder joint group have an equal length. Substrate cables connected to solder joints in the second solder joint group have an equal length.

Abstract translation: 芯片包括通过包装工艺包裹在一起的基底和模具。 对应于附接点的多个基板电缆布置在基板中。 在基板的底部的焊点基体中的焊接点包括沿着两条平行线布置的第一焊点组和第二焊点组。 与第一焊接组中的焊点相连的基板电缆具有相等的长度。 连接到第二焊接组中的焊点的基板电缆具有相等的长度。