公开(公告)号：US20240347439A1

公开(公告)日：2024-10-17

申请号：US18753091

申请日：2024-06-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shin-Puu JENG ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Feng-Cheng HSU ,  Shuo-Mao CHEN ,  Techi WONG

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/053 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15311

摘要： A chip package is provided. The chip package includes a substrate structure including: a redistribution structure having a conductive pad; and an insulating layer under the redistribution structure. The chip package includes a first chip over the redistribution structure. The chip package includes a second chip under the substrate structure. A top portion of the second chip extends into the insulating layer from a bottom surface of the insulating layer, the bottom surface faces away from the first chip, and a portion of the insulating layer is between the second chip and the redistribution structure. The chip package includes a first molding layer over the redistribution structure and the first chip. A first sidewall of the first molding layer and a second sidewall of the redistribution structure are substantially level with each other.

公开(公告)号：US20240332105A1

公开(公告)日：2024-10-03

申请号：US18295230

申请日：2023-04-03

申请人： NXP USA, Inc.

发明人： Namrata Kanth ,  Scott M. Hayes ,  Stephen Ryan Hooper ,  Chayathorn Saklang ,  Burton Jesse Carpenter

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L23/3135 ,  H01L21/565 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/16145 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/73215 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2224/8502 ,  H01L2924/1815

摘要： A multidevice package includes upper and lower surfaces with the lower surface disposed beneath a first die forming part of the package. The lower surface includes a first a set of electrical contacts and a recessed region with a second set of electrical contacts configured to allow a second die to be coupled to the lower surface and electrically coupled to the first die via the second set of contacts. The recessed region is sufficiently recessed to allow the package to be coupled to a mounting surface such as a printed circuit board via the first set of contacts while the second die remains suspended above the mounting surface.

公开(公告)号：US12087718B2

公开(公告)日：2024-09-10

申请号：US18300493

申请日：2023-04-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Horng Chang ,  Tin-Hao Kuo ,  Chen-Shien Chen ,  Yen-Liang Lin

IPC分类号： H01L23/00 ,  H01L25/00

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/11849 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/14051 ,  H01L2224/1412 ,  H01L2224/14152 ,  H01L2224/14153 ,  H01L2224/16056 ,  H01L2224/16059 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81345 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/2064 ,  H01L2924/384 ,  Y10T428/12493 ,  Y10T428/24479

摘要： The present disclosure relates to an integrated chip structure having a first substrate including a plurality of transistor devices disposed within a semiconductor material. An interposer substrate includes vias extending through a silicon layer. A copper bump is disposed between the first substrate and the interposer substrate. The copper bump has a sidewall defining a recess. Solder is disposed over the copper bump and continuously extending from over the copper bump to within the recess. A conductive layer is disposed between the first substrate and the interposer substrate and is separated from the copper bump by the solder.

公开(公告)号：US20240266324A1

公开(公告)日：2024-08-08

申请号：US18438638

申请日：2024-02-12

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Michael Kelly ,  Ronald Patrick Huemoeller ,  David Jon Hiner

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC分类号： H01L25/0655 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/14 ,  H01L25/50 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/29294 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/01014 ,  H01L2924/014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15738 ,  H01L2924/18161

摘要： Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.

公开(公告)号：US20240258258A1

公开(公告)日：2024-08-01

申请号：US18103698

申请日：2023-01-31

申请人： Taiwan Semiconductor Manufacturing Company

发明人： Shih-Cheng Chang ,  Yao-Chun Chuang

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/11011 ,  H01L2224/11334 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L2224/1413 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/20107

摘要： A substrate or IC chip is connected with a second substrate or IC chip. This entails disposing electrically conductive balls on electrical bonding pads of a surface of the substrate or IC chip to form a ball grid array (BGA) disposed on the surface of the substrate or IC chip, and electrically and mechanically connecting the surface of the substrate or IC chip to the second substrate or IC chip using the BGA. An underfill material may be disposed on the surface of the substrate or IC chip around bonds between the balls and the electrical bonding pads. There may be at least two different types of electrically conductive balls in the BGA, such as solder balls and copper-based balls.

公开(公告)号：US12051616B2

公开(公告)日：2024-07-30

申请号：US18298780

申请日：2023-04-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Der-Chyang Yeh

IPC分类号： H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/10 ,  H01L25/11 ,  H05K3/42 ,  H05K3/46

CPC分类号： H01L21/768 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/105 ,  H01L25/115 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/13099 ,  H01L2224/14135 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/92224 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/429 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2203/1316

摘要： Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

公开(公告)号：US20240222318A1

公开(公告)日：2024-07-04

申请号：US18608296

申请日：2024-03-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jing-Cheng LIN ,  Po-Hao TSAI

IPC分类号： H01L23/00 ,  B23K1/00 ,  H01L21/768 ,  H01L23/498 ,  B23K101/42

CPC分类号： H01L24/83 ,  B23K1/0016 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  B23K2101/42 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3841

摘要： A method of making a semiconductor device includes patterning a photoresist on a substrate to form a plurality of openings. A first opening has a first width, a second opening has a second width, smaller than the first width, and a third opening is between the first opening and the second opening and has a third width, different from the first width and the second width. The width is measured in a direction parallel to a top surface of the substrate. The method further includes plating a first conductive material into each opening of the plurality of openings in the photoresist. Plating the first conductive material includes plating of the first conductive material to a first height in the first opening, plating the first conductive material to a second height in the second opening, and plating the first conductive material to a third height in the third opening.

公开(公告)号：US12015023B2

公开(公告)日：2024-06-18

申请号：US17355433

申请日：2021-06-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shang-Yun Hou ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Hsien-Pin Hu ,  Yushun Lin ,  Heh-Chang Huang ,  Hsing-Kuo Hsia ,  Chih-Chieh Hung ,  Ying-Ching Shih ,  Chin-Fu Kao ,  Wen-Hsin Wei ,  Li-Chung Kuo ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC分类号： H01L25/00 ,  H01L21/48 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC分类号： H01L25/50 ,  H01L21/4803 ,  H01L21/4853 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2224/81

摘要： An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

公开(公告)号：US11961810B2

公开(公告)日：2024-04-16

申请号：US17352844

申请日：2021-06-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Wei Lin ,  Sheng-Yu Wu ,  Yu-Jen Tseng ,  Tin-Hao Kuo ,  Chen-Shien Chen

IPC分类号： H01L21/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/02 ,  H01L21/4853 ,  H01L21/76885 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0401 ,  H01L2224/05114 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/10125 ,  H01L2224/11013 ,  H01L2224/11019 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13551 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/81007 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/81895 ,  H01L2224/8192 ,  H01L2224/81948 ,  H01L2225/06513 ,  H01L2924/04941 ,  H01L2924/07025 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/35 ,  Y10T29/49144 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2224/13166 ,  H01L2924/00014 ,  H01L2224/13164 ,  H01L2924/00014 ,  H01L2224/81447 ,  H01L2924/00014 ,  H01L2224/81444 ,  H01L2924/00014 ,  H01L2224/81439 ,  H01L2924/00014 ,  H01L2224/81424 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/014 ,  H01L2224/13116 ,  H01L2924/014 ,  H01L2224/13686 ,  H01L2924/05432 ,  H01L2224/13686 ,  H01L2924/053 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/13012 ,  H01L2924/00012 ,  H01L2224/13005 ,  H01L2924/206 ,  H01L2224/13005 ,  H01L2924/207

摘要： An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

公开(公告)号：US20240006370A1

公开(公告)日：2024-01-04

申请号：US18213960

申请日：2023-06-26

申请人： STATS ChipPAC Semiconductor (Jiangyin) Co., LTD.

发明人： ZELONG YU ,  HONGDE DAI ,  JIAN XU

IPC分类号： H01L23/00 ,  H01L23/367 ,  H01L21/56

CPC分类号： H01L24/73 ,  H01L2224/92125 ,  H01L21/563 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13082 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/2929 ,  H01L2924/0665 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81193 ,  H01L2224/81191 ,  H01L2224/831 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L23/3675

摘要： The present invention provides a chip packaging structure having a heat dissipation plate and a manufacturing method thereof. The packaging structure includes a substrate; at least one chip, disposed on a first surface of the substrate; the heat dissipation plate is bonded to the first surface, the heat dissipation plate and the substrate form a cavity in a surrounding manner for holding the chip therein, the heat dissipation plate and the chip are connected by at least one fixed connector, a thermal interface material is filled in a region among the heat dissipation plate, the chip and the fixed connector, and a connection strength between the fixed connector and the chip or the heat dissipation plate is greater than a connection strength between the thermal interface material and the chip or the heat dissipation plate. Thus, the connection strength between the chip and the heat dissipation plate is increased.