公开(公告)号：US3622985A

公开(公告)日：1971-11-23

申请号：US3622985D

申请日：1969-11-25

Applicant: IBM

Inventor： AYLING JOHN K ,  LEE HUA-TUNG

IPC: G06F11/10 ,  G06F12/16 ,  H03M13/00 ,  H03M13/19 ,  G06F11/12 ,  G08C25/00

CPC classification number: H03M13/19

Abstract: Errors in transmitted shortened cyclic code words are detected and corrected by unusually simple apparatus at a receiver and transmitter connected together by a bus. A 72-bit parallel code word, actually comprising a 64-bit data portion and an eight bit checking portion, is conceptually expanded and treated as if it were 108 bits long. At both the transmitter and receiver, the word is split into four sequential groups and sent to an eightposition parallel feedback shift register via an 18-bit bus and intermediate circuits. Each bit on the bus is assigned a channel and the register positions are connected to selected channels through summing circuits, and to each other through feedback circuits, of varying complexity. At the transmitter, the final contents of the register are the checking portion of the code word. At the receiver, if there is an error, the final contents of the shift register indicate which bit in the data portion of the code word must be corrected. The eighteen bits on the bus are connected to selected ones of 27 conceptual channels of which 18 are real (connected to the bus) and nine are phantoms (not connected to anything). While no summing circuit connections are required for the phantom channels, each one of the 27 conceptual channels nevertheless has associated with it a known number of circuit connections. The amount of hardware is greatly reduced by connecting to the bus those conceptual channels requiring the least number of circuit connections and designating as phantoms those conceptual channels which would have required the most summing circuit connections. The total complexity of the feedback circuits and associated error location and correction circuits are similarly lessened.

公开(公告)号：US3688280A

公开(公告)日：1972-08-29

申请号：US3688280D

申请日：1970-09-22

Applicant: IBM

Inventor： AYLING JOHN K ,  MOORE RICHARD D

IPC: G11C11/411 ,  G11C11/414 ,  G11C11/415 ,  G11C7/00 ,  G11C5/02 ,  G11C11/40

CPC classification number: G11C11/4116 ,  G11C11/414 ,  G11C11/415

Abstract: A monolithic integrated semiconductor circuit in which both the memory array proper and the addressing and decoding support circuitry are subjected to two power levels, i.e. a low power level when the memory array is in the non-selected or inactive state and a higher level of power necessary to render the decode and address circuitry operational and to make the lines of the array selected by said support circuitry operational for reading and writing into the memory. In order that the time required for the selection of a given line in the memory array, either a row or a column, be held to a minimum, decoding means provide an output which applies to all of the gates associated with each of the rows and/or columns, the preselected patterns required to activate a row or column during the low power or inactive state. Then, during the active state when higher power is applied, the decode circuitry functions to remove the preselected signal necessary to activate a row or column from all of the gates except the gate associated with the column or row to be activated. By functioning in this manner, the circuitry of the present invention avoids a time lag when the higher level is applied which would otherwise be necessary in order to bring the preselected input signal applied to the selected gate up to the level necessary to activate the selected column or row.

Abstract translation: 一种单片集成半导体电路，其中存储器阵列本身和寻址和解码支持电路都经受两个功率电平，即，当存储器阵列处于非选择或不活动状态时的低功率电平和更高的功率电平 必须使解码和地址电路可操作并且使由所述支持电路选择的阵列的行可操作用于读取和写入存储器。