公开(公告)号：US3901814A

公开(公告)日：1975-08-26

申请号：US48350974

申请日：1974-06-27

Applicant: IBM

Inventor： DAVIS DONALD E ,  HABEGGER MILLARD A ,  MOORE RICHARD D ,  WEBER EDWARD V ,  WOODARD OLLIE C

IPC: G05D3/12 ,  H01J37/304 ,  H01L21/027 ,  H01J37/00

CPC classification number: H01J37/304

Abstract: A square-shaped beam of charged particles is passed over a registration mark, which is formed by a depression or a rise in the surface of a semiconductor wafer. When the beam passes over one edge of the mark, a positive peak signal is produced from a pair of diode detectors located with their surfaces orthogonal to the direction of the beam scan and a negative peak signal is produced when the beam passes over the other edge of the mark. The amplitudes of these peak signals are balanced so that they are substantially the same irrespective of the location of each of the diode detectors relative to the mark in comparison with the location of the other of the diode detectors relative to the mark. These peak signals are compared with positive and negative threshold signals in comparators with an output signal being produced from each of the comparators when its threshold signal is crossed. This enables location of each of the marks to be determined. The positive and negative threshold signals are set during the prior scan with the scans being in opposite directions. The peak to peak amplitude across the registration mark in a particular area is sampled during the first scan and used to provide an automatic gain factor for the remainder of the scans across the mark so that a substantially constant peak amplitude signal is transmitted to the comparators.

公开(公告)号：US3688280A

公开(公告)日：1972-08-29

申请号：US3688280D

申请日：1970-09-22

Applicant: IBM

Inventor： AYLING JOHN K ,  MOORE RICHARD D

IPC: G11C11/411 ,  G11C11/414 ,  G11C11/415 ,  G11C7/00 ,  G11C5/02 ,  G11C11/40

CPC classification number: G11C11/4116 ,  G11C11/414 ,  G11C11/415

Abstract: A monolithic integrated semiconductor circuit in which both the memory array proper and the addressing and decoding support circuitry are subjected to two power levels, i.e. a low power level when the memory array is in the non-selected or inactive state and a higher level of power necessary to render the decode and address circuitry operational and to make the lines of the array selected by said support circuitry operational for reading and writing into the memory. In order that the time required for the selection of a given line in the memory array, either a row or a column, be held to a minimum, decoding means provide an output which applies to all of the gates associated with each of the rows and/or columns, the preselected patterns required to activate a row or column during the low power or inactive state. Then, during the active state when higher power is applied, the decode circuitry functions to remove the preselected signal necessary to activate a row or column from all of the gates except the gate associated with the column or row to be activated. By functioning in this manner, the circuitry of the present invention avoids a time lag when the higher level is applied which would otherwise be necessary in order to bring the preselected input signal applied to the selected gate up to the level necessary to activate the selected column or row.

Abstract translation: 一种单片集成半导体电路，其中存储器阵列本身和寻址和解码支持电路都经受两个功率电平，即，当存储器阵列处于非选择或不活动状态时的低功率电平和更高的功率电平 必须使解码和地址电路可操作并且使由所述支持电路选择的阵列的行可操作用于读取和写入存储器。