公开(公告)号：US3601800A

公开(公告)日：1971-08-24

申请号：US3601800D

申请日：1969-09-30

Applicant: IBM

Inventor： LEE HUA-TUNG

IPC: G06F11/10 ,  G06F12/16 ,  H03M13/00 ,  H04L1/00 ,  G08C25/00 ,  H04L1/10

CPC classification number: H04L1/0057

Abstract: Data signals are encoded in an (n,k) cyclic code and checked for errors and corrected. The encoding and correction decoding apparatus includes an n-k stage parallel input parallel feedback shift register adapted to process the data digit signals in groups of c digits where the number c is greater than n-k. An example of implementation is disclosed for the specific case: n 72, k 64, and c 18, illustrating that encoding and/or error check decoding are completed in only 4 ( n/c) parallel shifts and that error correction decoding is accomplished in a maximum of only 3 additional parallel shifts timed to coincide with the handling of the data signals.

公开(公告)号：US3443195A

公开(公告)日：1969-05-06

申请号：US3443195D

申请日：1967-09-14

Applicant: IBM

Inventor： HOFFMAN HARRY S JR ,  LEE HUA-TUNG

IPC: G05F1/62 ,  H02M3/28 ,  H02M3/335 ,  H02M3/337 ,  H02M3/02

CPC classification number: H02M3/28 ,  G05F1/62 ,  H02M3/33569 ,  H02M3/3378

公开(公告)号：US3911401A

公开(公告)日：1975-10-07

申请号：US36704673

申请日：1973-06-04

Applicant: IBM

Inventor： LEE HUA-TUNG

IPC: G06F12/08 ,  G06F12/12 ,  G06F13/00

CPC classification number: G06F12/0897

Abstract: A hierarchial memory/storage system in which the data is transferred between a high speed local storage, responsive to the processing unit of the computer, and a plurality of higher levels of larger low speed storage wherein data available to the central processing unit is shifted between the various levels of the hierarchial system in a highly efficient manner. In operation, the system in responding to the central processing unit for making available data in the high speed lowest hierarchial level, will seek out the instant lowest buffer memory/storage level containing the required information, form a path of expendable blocks or page frames in the various buffer levels from the adjacent lower level down to the H1 level, shift any updated information in the path of expendable pages to the off-the-path pages at appropriate higher levels utilizing the successively lengthened cleared upper path for forward and rearward transfer of blocks or pages within the memory system, and subsequently, when the complete clear path of expendable blocks or page frames is formed, transfer and filter the called-for data segments through the path to the level of the hierarchial memory responsive to the processing unit of the computer.

Abstract translation: 分层存储/存储系统，其中数据在响应于计算机的处理单元的高速本地存储器和多个较高级别的较大的低速存储器之间传送，其中可用于中央处理单元的数据在 分层次制度的各个层次都以高效的方式进行。 在操作中，响应中央处理单元的系统以高速最低层次级别提供可用数据，将寻找包含所需信息的即时最低缓冲存储/存储级别，形成可消耗块或页框的路径 从相邻较低级别到H1级别的各种缓冲器级别，使用连续延长的清除的上部路径将可消耗页面的路径中的任何更新的信息移动到适当的较高级别的路外页面，用于向前和向后传送 存储器系统内的块或页面，随后，当形成消耗性块或页面帧的完整清晰路径时，响应于处理单元将被调用的数据段通过路径传递到层次存储器的级别 电脑

公开(公告)号：US3893080A

公开(公告)日：1975-07-01

申请号：US37521173

申请日：1973-06-29

Applicant: IBM

Inventor： HO ALLEN P ,  LEE HUA-TUNG

IPC: G06K9/00 ,  G06K9/46 ,  G06K9/12

CPC classification number: G06K9/4638 ,  G06K9/00067

Abstract: A system for detecting bifurcations and ridge endings (minutiae) in a fingerprint or on similar patterns in which two lines merge into one. The print is optically scanned, converted into electrical signals and entered into a novel continuity logic network. The presence of a bifurcation in the network results in three distinct outputs on the periphery of the network from at least two sides. The split in the bifurcation may also be detected by reversing the polarity of the electrical signals and detecting a single output. Means are also provided for ensuring that a single bifurcation is detected only once. Ridge endings are treated as reverse-polarity bifurcations and can be detected by the same system elements.

Abstract translation: 用于检测指纹中的分叉和脊端（细节）的系统，或者将两条线合并成一个的相似图案。 打印件被光学扫描，转换成电信号并进入一个新颖的连续性逻辑网络。 在网络中存在分支，从至少两侧在网络的外围产生三个不同的输出。 也可以通过反转电信号的极性并检测单个输出来检测分叉中的分割。 还提供了用于确保单个分叉仅被检测到一次的手段。 脊线端点被视为反极性分岔，并且可以由相同的系统元件来检测。

公开(公告)号：US3622985A

公开(公告)日：1971-11-23

申请号：US3622985D

申请日：1969-11-25

Applicant: IBM

Inventor： AYLING JOHN K ,  LEE HUA-TUNG

IPC: G06F11/10 ,  G06F12/16 ,  H03M13/00 ,  H03M13/19 ,  G06F11/12 ,  G08C25/00

CPC classification number: H03M13/19

Abstract: Errors in transmitted shortened cyclic code words are detected and corrected by unusually simple apparatus at a receiver and transmitter connected together by a bus. A 72-bit parallel code word, actually comprising a 64-bit data portion and an eight bit checking portion, is conceptually expanded and treated as if it were 108 bits long. At both the transmitter and receiver, the word is split into four sequential groups and sent to an eightposition parallel feedback shift register via an 18-bit bus and intermediate circuits. Each bit on the bus is assigned a channel and the register positions are connected to selected channels through summing circuits, and to each other through feedback circuits, of varying complexity. At the transmitter, the final contents of the register are the checking portion of the code word. At the receiver, if there is an error, the final contents of the shift register indicate which bit in the data portion of the code word must be corrected. The eighteen bits on the bus are connected to selected ones of 27 conceptual channels of which 18 are real (connected to the bus) and nine are phantoms (not connected to anything). While no summing circuit connections are required for the phantom channels, each one of the 27 conceptual channels nevertheless has associated with it a known number of circuit connections. The amount of hardware is greatly reduced by connecting to the bus those conceptual channels requiring the least number of circuit connections and designating as phantoms those conceptual channels which would have required the most summing circuit connections. The total complexity of the feedback circuits and associated error location and correction circuits are similarly lessened.