公开(公告)号：US3665174A

公开(公告)日：1972-05-23

申请号：US3665174D

申请日：1968-09-03

Applicant: IBM

Inventor： BOURICIUS WILLARD G ,  CARTER WILLIAM C ,  DUKE KEITH A ,  ROTH JOHN P ,  SCHNEIDER PETER R

IPC: G06F11/20 ,  G06F11/04

CPC classification number: G06F11/2028 ,  G06F11/2025 ,  G06F11/2038 ,  G06F11/2041

Abstract: The error tolerant arithmetic logical unit is divided into vertical bit-planes which are relatively independent, being coupled mainly for the purposes of shifts and carry propagation. The system tolerates failures and still functions correctly by reconfiguring the unit through the control of interplane connections. By inserting a spare bit-plane into the system and switching between bit-planes to bypass a failed plane, the effect of the failed plane or of a failure in a position of control logic can be eliminated.

公开(公告)号：US3585378A

公开(公告)日：1971-06-15

申请号：US3585378D

申请日：1969-06-30

Applicant: IBM

Inventor： BOURICIUS WILLARD G ,  DUKE KEITH A

IPC: G06F11/10 ,  G06F12/16 ,  G11C29/00 ,  H03K13/34

CPC classification number: G06F11/1016 ,  G06F11/1032

Abstract: A method and apparatus for detecting errors occurring as a result of faulty memory operation. By storing every data word in an addressable memory at an address therein having a parity with a fixed predetermined relationship to the parity of the said data word, errors occurring in the memory may be detected. By incorporating an extra bit in the memory word, the error can be isolated and by incorporating two extra bits, double word readout errors may be detected.

公开(公告)号：US3665173A

公开(公告)日：1972-05-23

申请号：US3665173D

申请日：1968-09-03

Applicant: IBM

Inventor： BOURICIUS WILLARD G ,  CARTER WILLIAM C ,  ROTH JOHN P ,  SCHNEIDER PETER R

IPC: G05D1/00 ,  G06F11/18 ,  G06F11/20 ,  H03K19/003 ,  G06F11/04

CPC classification number: G06F11/181 ,  G05D1/0077 ,  G06F11/183 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2028 ,  G06F11/2041 ,  G06F11/2043 ,  H03K19/00392

Abstract: A computer system of the standby redundancy type including three active logic modules and at least one spare module, characterized by the provision of triple modular redundancy means for correcting and locating the failure of a first one of said active logic modules, in combination with sparing means for reconfiguring the system to by-pass the faulty module and to substitute the spare module therefor. The invention is further characterized by the provision of means for reintroducing the first module into the system upon the detection of failure of another active module.

公开(公告)号：US3665175A

公开(公告)日：1972-05-23

申请号：US3665175D

申请日：1968-09-03

Applicant: IBM

Inventor： BOURICIUS WILLARD G ,  CARTER WILLIAM C ,  ROTH JOHN P ,  SCHNEIDER PETER R

IPC: G11C29/00

CPC classification number: G11C29/76

Abstract: Mapping control means for achieving error toleration in computer addressing circuitry including switching means for connecting an address register with the effective address register of a basic operating module. The switching means are operable by a blocking register and at least one status register to control the mapping connections in a given manner. The invention is characterized by the provision of an address blocking register and a mask register that process a sequence of failed addresses and insert corresponding control instructions in the blocking and status registers so that the switching means dynamically excludes access to the memory area affected by the faulty address circuitry.