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    Parity checked shift register counters
    1.
    发明授权
    Parity checked shift register counters 失效
    奇妙的检查移位寄存器计数器

    公开(公告)号：US3701892A

    公开(公告)日：1972-10-31

    申请号：US3701892D

    申请日：1970-12-17

    Applicant: IBM

    Inventor： CARTER WILLIAM C ,  SCHNEIDER PETER R

    IPC: G06F11/10 ,  H03K21/40

    CPC classification number: G06F11/10 ,  H03K21/40

    Abstract: The present invention relates to a family of parity-checked shift register counters having a counting period not determined by a power of 2 wherein the power is determined by the number of shift register stages. It will be apparent that the range of the counter is effected by the number of stages but not necessarily the actual count. The family of counters is further characterized in that either odd or even parity may be designed into the output pattern of said counter, which parity will be automatically maintained for all binary-bit patterns to produce. The family of counters is further characterized in that they require only N+6 logic circuits wherein there are N shift register stages, four 2input exclusive ORs and 2 N input AND circuits. The counters are also characterized in that they are self testing. That is, all components are tested for faults in normal operations.

    Abstract translation: 本发明涉及一种奇偶校验移位寄存器计数器系列，其具有不由2的功率确定的计数周期，其中功率由移位寄存器级的数量确定。 显而易见的是，计数器的范围是通过阶数来实现的，但不一定是实际计数。 计数器系列的特征还在于奇数或偶校验可被设计成所述计数器的输出模式，对于所有二进制位模式产生，奇偶校验将被自动维持。 计数器系列的特征还在于它们仅需要N + 6逻辑电路，其中存在N个移位寄存器级，四个2输入异或和2N输入与电路。 柜台的特点还在于自检。 也就是说，所有组件都在正常操作中测试故障。

    Self-checking error checker for parity coded data
    3.
    发明授权
    Self-checking error checker for parity coded data 失效
    自检错误检查器，用于奇偶校验数据

    公开(公告)号：US3602886A

    公开(公告)日：1971-08-31

    申请号：US3602886D

    申请日：1968-07-25

    Applicant: IBM

    Inventor： CARTER WILLIAM C ,  SCHNEIDER PETER R

    IPC: G06F11/10 ,  H03K13/34 ,  H03K5/18 ,  H04L1/10

    CPC classification number: G06F11/10

    Abstract: A series of self-checking error checking circuits are disclosed for checking conventional parity coded data lines. The data signal set includes any logical combination of binary ''''1''s'''' and ''''0''s'''' and at least one parity bit. The circuit comprises at least 2 exclusive OR tree circuits wherein each tree obtains its inputs from different input lines whereby complementing outputs are produced by the two tree circuits for any correct signal set and wherein the checker is error free. Any error in the data will cause the two outputs to be the same. Malfunctions or failures in the checking circuit are checked by certain legitimate code signals which similarly cause an error representation in the output of the checker.

    Self-checking error checker for two-rail coded data
    5.
    发明授权
    Self-checking error checker for two-rail coded data 失效
    自检错误检查器，用于两轨编码数据

    公开(公告)号：US3559167A

    公开(公告)日：1971-01-26

    申请号：US3559167D

    申请日：1968-07-25

    Applicant: IBM

    Inventor： CARTER WILLIAM C ,  DUKE KEITH A ,  SCHNEIDER PETER R

    IPC: G06F11/16 ,  H03K13/22

    CPC classification number: H03K19/00392 ,  G06F11/10

    Abstract: A SERIES OF SELF-CHECKING ERROR CHECKING CIRCUITS ARE DISCLOSED FOR CHECKING TWO-RAIL LOGIC CODED DATA LINES. THE DATA LINES ARE ARRANGED AS N PAIRS OF TWO-RAIL GROUPS. ONE FORM OF THE CHECKER COMPRISES N-1 BASIC TWO OUTPUT BLOCKS CONNECTED IN A GENERAL TREE CONFIGURATION ACROSS THE TWO-RAIL DATA LINES. EACH OF SAID BASIC BLOCKS HAS TWO NORMALLY COMPLEMENTARY OUTPUT LINES AND THE LAST STAGE OF THE CHECKER IS A SINGLA BASIC BLOCK. IF AN INVAID CODE IS RECEIVED, THE TWO OUTPUTS WILL BE IDENTICAL. MALFUNCTIONS OR FAILURES IN THE CHECKING CIRCUIT ARE CHECKED BY CERTAIN LEGITIMATE CODE SIGNALS WHICH SIMILARLY CAUSE AN ERROR REPRESENTATION IN THE OUTPUT OF THE CHECKER WHEREBY BOTH OUTPUTS WILL BE IDENTICAL.

    Dynamic storage address blocking to achieve error toleration in the addressing circuitry
    6.
    发明授权
    Dynamic storage address blocking to achieve error toleration in the addressing circuitry 失效
    动态存储地址阻塞以在寻址电路中实现错误抑制

    公开(公告)号：US3665175A

    公开(公告)日：1972-05-23

    申请号：US3665175D

    申请日：1968-09-03

    Applicant: IBM

    Inventor： BOURICIUS WILLARD G ,  CARTER WILLIAM C ,  ROTH JOHN P ,  SCHNEIDER PETER R

    IPC: G11C29/00

    CPC classification number: G11C29/76

    Abstract: Mapping control means for achieving error toleration in computer addressing circuitry including switching means for connecting an address register with the effective address register of a basic operating module. The switching means are operable by a blocking register and at least one status register to control the mapping connections in a given manner. The invention is characterized by the provision of an address blocking register and a mask register that process a sequence of failed addresses and insert corresponding control instructions in the blocking and status registers so that the switching means dynamically excludes access to the memory area affected by the faulty address circuitry.

    System use of self-testing checking circuits
    7.
    发明授权
    System use of self-testing checking circuits 失效
    自检检查电路的系统使用

    公开(公告)号：US3634665A

    公开(公告)日：1972-01-11

    申请号：US3634665D

    申请日：1969-06-30

    Applicant: IBM

    Inventor： CARTER WILLIAM C ,  SCHNEIDER PETER R

    IPC: H03M13/00 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F15/16

    CPC classification number: G01R31/31835 ,  G01R31/3187 ,  G06F11/1032

    Abstract: A self-testing error-checking system for inclusion in a computer comprising a plurality of self-testing check circuits, each said circuit having a two-rail complementary output whenever both the circuits being tested and the checking circuit is operating properly and an identical output on each of the two output lines whenever a fault is detected. The improvement which comprises reduction checking means connected to all said two-rail outputs from said checking circuits, and means connected to the output of said reduction checker means for at least indicating that a failure has occurred. The output of said reduction checker itself is two rail and complementary when all inputs are correct and the checker itself is operating properly. The output of the present checking system may be connected to a computer interrupt circuit or to a visual logout means. Alternatively, the system output may be utilized to effect automatic self-repair.

    Abstract translation: 一种用于包含在包括多个自测试检查电路的计算机中的自检错误检查系统，每当所述两个电路被测试且检查电路正常工作并且相同的输出时，每个所述电路具有双轨互补输出 每当检测到故障时，在两条输出线中的每一条上。 所述改进包括从所述检查电路连接到所有所述两轨输出的减小检查装置，以及连接到所述缩小检查装置的输出的装置，用于至少指示发生故障。 当所有输入正确并且检验器本身正常运行时，所述还原检查器本身的输出是两个轨道和互补的。 本检查系统的输出可以连接到计算机中断电路或视觉注销装置。 或者，可以利用系统输出来实现自动自修复。

    Self-checking error checker for kappa-out-of-nu coded data
    8.
    发明授权
    Self-checking error checker for kappa-out-of-nu coded data 失效
    自我检测错误检查器，用于KAPPA-OUT-OF-NU编码数据

    公开(公告)号：US3559168A

    公开(公告)日：1971-01-26

    申请号：US3559168D

    申请日：1968-07-25

    Applicant: IBM

    Inventor： CARTER WILLIAM C ,  DUKE KEITH A ,  SCHNEIDER PETER R

    IPC: G06F11/08 ,  H03K13/32 ,  G08C25/00

    CPC classification number: G06F11/085

    Abstract: A SERIES OF SELF-CHECKING ERROR CHECKING CIRCUITS ARE DISCLOSED FOR CHECKING K-OUT-OF-N CODED DATA LINES. THE N LINES ARE BROKEN INTO TWO, PREFERABLY EQUAL, GROUPS. A LOGIC EQUATION IS DERIVED FOR EACH GROUP OF LINES WHEREBY, WITH ANY K-OUT-OF-N CODED DATA SIGNALS APPLIED TO THE INPUT, AT LEAST TWO COMPLEMENTARY OUTPUT SIGNALS ARE PRODUCED. ANY ERROR APPEARING IN THE RECEIVED CODE WILL BE INDICATED AS SUCH BY NON-COMPLEMENTARY OUTPUTS FROM

    THE CHECKER IN THE OUTPUT OF THE CHECKER. MALFUNCTIONS OR FAILURES IN THE CHECKING CIRCUIT ARE CHECKED BY CERTAIN LEGITIMATE CODE SIGNALS WHICH SIMILARLY CAUSE AN ERROR REPRESENTATION IN NON-COMPLEMENTARY OUTPUTS AT THE OUTPUT OF THE CHECKER.

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