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    Self-checking error checker for kappa-out-of-nu coded data
    1.
    发明授权
    Self-checking error checker for kappa-out-of-nu coded data 失效
    自我检测错误检查器，用于KAPPA-OUT-OF-NU编码数据

    公开(公告)号：US3559168A

    公开(公告)日：1971-01-26

    申请号：US3559168D

    申请日：1968-07-25

    Applicant: IBM

    Inventor： CARTER WILLIAM C ,  DUKE KEITH A ,  SCHNEIDER PETER R

    IPC: G06F11/08 ,  H03K13/32 ,  G08C25/00

    CPC classification number: G06F11/085

    Abstract: A SERIES OF SELF-CHECKING ERROR CHECKING CIRCUITS ARE DISCLOSED FOR CHECKING K-OUT-OF-N CODED DATA LINES. THE N LINES ARE BROKEN INTO TWO, PREFERABLY EQUAL, GROUPS. A LOGIC EQUATION IS DERIVED FOR EACH GROUP OF LINES WHEREBY, WITH ANY K-OUT-OF-N CODED DATA SIGNALS APPLIED TO THE INPUT, AT LEAST TWO COMPLEMENTARY OUTPUT SIGNALS ARE PRODUCED. ANY ERROR APPEARING IN THE RECEIVED CODE WILL BE INDICATED AS SUCH BY NON-COMPLEMENTARY OUTPUTS FROM

    THE CHECKER IN THE OUTPUT OF THE CHECKER. MALFUNCTIONS OR FAILURES IN THE CHECKING CIRCUIT ARE CHECKED BY CERTAIN LEGITIMATE CODE SIGNALS WHICH SIMILARLY CAUSE AN ERROR REPRESENTATION IN NON-COMPLEMENTARY OUTPUTS AT THE OUTPUT OF THE CHECKER.

    Error correction system for use with a rotational single-error correction, double-error detection hamming code
    2.
    发明授权
    Error correction system for use with a rotational single-error correction, double-error detection hamming code 失效
    错误校正系统，具有旋转单一错误校正，双重错误检测命令代码

    公开(公告)号：US3697949A

    公开(公告)日：1972-10-10

    申请号：US3697949D

    申请日：1970-12-31

    Applicant: IBM

    Inventor： CARTER WILLIAM C ,  DUKE KEITH A ,  JESSEP DONALD C JR

    IPC: G06F11/10 ,  G06F11/12

    CPC classification number: G06F11/1012

    Abstract: The present invention relates to a highly-efficient system for performing single-error correction when utilized with a memory system including a memory equipped with error-detection circuitry for use with rotationally-encoded, single-error correction, double-error detection Hamming coded data wherein said memory system circuitry includes means for developing syndrome bits, the patterns of which indicate faulty operation. Hardware is included for first identifying the specific byte which contains the error and still further hardware is provided to locate the particular bit which is erroneous. By efficient use of the rotational characteristic of the present coding scheme, correction is made only when necessary and only that hardware necessary to correct a single byte is provided in the correction circuitry.

    Abstract translation: 本发明涉及一种用于执行单一错误校正的高效系统，该系统与存储器系统一起使用，存储器系统包括配备有用于旋转编码的单错误校正，双错误检测汉明编码数据的错误检测电路的存储器 其中所述存储器系统电路包括用于开发校正子位的装置，其模式指示故障操作。 包括硬件，用于首先识别包含错误的特定字节，并且还提供进一步的硬件来定位错误的特定位。 通过有效利用当前编码方案的旋转特性，仅在必要时进行校正，并且仅在校正电路中提供校正单个字节所需的硬件。

    Error detection scheme for memories
    4.
    发明授权
    Error detection scheme for memories 失效
    存储器错误检测方案

    公开(公告)号：US3585378A

    公开(公告)日：1971-06-15

    申请号：US3585378D

    申请日：1969-06-30

    Applicant: IBM

    Inventor： BOURICIUS WILLARD G ,  DUKE KEITH A

    IPC: G06F11/10 ,  G06F12/16 ,  G11C29/00 ,  H03K13/34

    CPC classification number: G06F11/1016 ,  G06F11/1032

    Abstract: A method and apparatus for detecting errors occurring as a result of faulty memory operation. By storing every data word in an addressable memory at an address therein having a parity with a fixed predetermined relationship to the parity of the said data word, errors occurring in the memory may be detected. By incorporating an extra bit in the memory word, the error can be isolated and by incorporating two extra bits, double word readout errors may be detected.

    Error tolerant read-only storage system
    5.
    发明授权
    Error tolerant read-only storage system 失效
    错误的只读存储系统

    公开(公告)号：US3576982A

    公开(公告)日：1971-05-04

    申请号：US3576982D

    申请日：1968-12-16

    Applicant: IBM

    Inventor： DUKE KEITH A

    IPC: G06F12/16 ,  E04H6/26 ,  G06F11/10 ,  G11C29/00 ,  G06F11/00

    CPC classification number: G11C29/74 ,  E04H6/26 ,  G06F11/1008 ,  G06F11/1032

    Abstract: A read-only storage system wherein each data word is stored twice, once in its true form and once in its complement form. Said two data words are further stored at complementary addresses and means are provided upon readout of any data word for detecting a system error. Said means being further operative to automatically access an address complementary to the one currently being utilized for reading out the same data word in the complementary form at said complementary address.

    System for translating to and from single error correction-double error detection hamming code and byte parity code
    7.
    发明授权
    System for translating to and from single error correction-double error detection hamming code and byte parity code 失效
    用于转换和从单个错误校正双重错误检测的系统命令代码和字节奇偶性代码

    公开(公告)号：US3648239A

    公开(公告)日：1972-03-07

    申请号：US3648239D

    申请日：1970-06-30

    Applicant: IBM

    Inventor： CARTER WILLIAM C ,  DUKE KEITH A ,  JESSEP DONALD C JR

    IPC: G06F11/10 ,  G08C25/00 ,  G06F11/00

    CPC classification number: G06F11/1012 ,  G06F11/10

    Abstract: An SEC/DED error detection and data translation mechanism is described. By the use of unique circuit design features, the same logical circuitry is capable of automatically taking Hamming encoded data from memory and parity encoding same for transmission elsewhere in the system as well as forming the necessary syndromes for purposes of error detection and correction. The same circuitry is capable of receiving encoded data from elsewhere in the system, first checking for any parity error and, if parity is proper, will generate the necessary Hamming check bits for storing in the memory together with the data information. The disclosed circuitry, by means of the unique partitioning thereof, separates the error detection and correction functions. It also generates parity bits essentially in parallel with error detection after a memory read cycle with the result that the data is propagated through the correction circuitry only when a single data bit error is detected.

    Abstract translation: 描述了SEC / DED错误检测和数据转换机制。 通过使用独特的电路设计特征，相同的逻辑电路能够自动地将来自存储器和奇偶校验编码的Hamming编码数据从系统中的其他地方传输，并形成用于错误检测和校正的必要的校验子。 相同的电路能够从系统的其他地方接收编码的数据，首先检查任何奇偶校验错误，并且如果奇偶校验是正确的，则将产生用于与数据信息一起存储在存储器中的必要的汉明校验位。 通过其独特的划分，所公开的电路分离出错误检测和校正功能。 它还在存储器读取周期之后基本上与错误检测并行地生成奇偶校验位，结果是仅当检测到单个数据位错误时，数据被传播通过校正电路。

    Self-checking error checker for two-rail coded data
    8.
    发明授权
    Self-checking error checker for two-rail coded data 失效
    自检错误检查器，用于两轨编码数据

    公开(公告)号：US3559167A

    公开(公告)日：1971-01-26

    申请号：US3559167D

    申请日：1968-07-25

    Applicant: IBM

    Inventor： CARTER WILLIAM C ,  DUKE KEITH A ,  SCHNEIDER PETER R

    IPC: G06F11/16 ,  H03K13/22

    CPC classification number: H03K19/00392 ,  G06F11/10

    Abstract: A SERIES OF SELF-CHECKING ERROR CHECKING CIRCUITS ARE DISCLOSED FOR CHECKING TWO-RAIL LOGIC CODED DATA LINES. THE DATA LINES ARE ARRANGED AS N PAIRS OF TWO-RAIL GROUPS. ONE FORM OF THE CHECKER COMPRISES N-1 BASIC TWO OUTPUT BLOCKS CONNECTED IN A GENERAL TREE CONFIGURATION ACROSS THE TWO-RAIL DATA LINES. EACH OF SAID BASIC BLOCKS HAS TWO NORMALLY COMPLEMENTARY OUTPUT LINES AND THE LAST STAGE OF THE CHECKER IS A SINGLA BASIC BLOCK. IF AN INVAID CODE IS RECEIVED, THE TWO OUTPUTS WILL BE IDENTICAL. MALFUNCTIONS OR FAILURES IN THE CHECKING CIRCUIT ARE CHECKED BY CERTAIN LEGITIMATE CODE SIGNALS WHICH SIMILARLY CAUSE AN ERROR REPRESENTATION IN THE OUTPUT OF THE CHECKER WHEREBY BOTH OUTPUTS WILL BE IDENTICAL.

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