公开(公告)号：US3668522A

公开(公告)日：1972-06-06

申请号：US3668522D

申请日：1968-12-09

Applicant: IBM

Inventor： GHAFGHAICHI MAJID

IPC: G01R29/02 ,  G01R31/26 ,  G01R31/22 ,  G01R27/04

CPC classification number: G01R31/2608 ,  G01R29/02

Abstract: Method and apparatus for characterizing the dynamic input impedance of a test element by measuring the rise-time degradation of an input waveform. A pulse having a very fast rise-time is supplied by a pulse generator and transmitted down two branches of a balanced transmission line. One leg of the balanced transmission line is connected to a sensing means while the other leg of the balanced transmission line is connected to a test element as well as the sensing means. Thus, the sensing means would receive two identical pulses but for the rise-time degradation of the pulse connected to the test element. The test element is characterized on the basis of this rise-time degradation.

Abstract translation: 通过测量输入波形的上升时间劣化来表征测试元件的动态输入阻抗的方法和装置。 具有非常快的上升时间的脉冲由脉冲发生器提供并且被传送到平衡传输线的两个分支。 平衡传输线的一条腿连接到感测装置，而平衡传输线的另一条腿连接到测试元件以及感测装置。 因此，感测装置将接收两个相同的脉冲，但是对于连接到测试元件的脉冲的上升时间劣化。 测试元件的特征在于这种上升时间退化。

公开(公告)号：US3922184A

公开(公告)日：1975-11-25

申请号：US42788773

申请日：1973-12-26

Applicant: IBM

Inventor： BAKER THEODORE H ,  GHAFGHAICHI MAJID

IPC: H05K3/46 ,  H01L21/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/31 ,  H01L21/316 ,  H01L21/3213 ,  H01L21/308

CPC classification number: H01L21/31 ,  H01L21/00 ,  H01L21/316

Abstract: In the fabrication of integrated circuits, a method of forming openings through an insulative layer wherein a plurality of openings being formed through said insulative layer are subjected to two separate etching steps in order to insure that the opening is made. In the method, a layer of electrically insulative material is formed on a substrate. The layer is covered with a first photoresist mask having a plurality of openings. Then, a plurality of openings through the insulative layer coincident with the mask openings is made by applying a chemical etchant through the photoresist mask. The second photoresist mask having a plurality of openings coincident with the openings in the insulative layer is then formed on said layer; these openings in the second photoresist mask have smaller lateral dimensions than the openings in the insulative layer. Thus, the sides of the openings in the insulative layer are masked by photoresist. The chemical etchant is reapplied through the second photoresist mask. In this reapplication, any openings which may not have been fully etched through the insulative layer in the first etching step are now made. On the other hand, because the sides of completed openings are already masked by photoresist, there is no possibility of the reapplied etchant etching through the sides of such completed holes to overetch such holes.

Abstract translation: 在集成电路的制造中，通过绝缘层形成开口的方法，其中通过所述绝缘层形成的多个开口经受两个单独的蚀刻步骤，以确保形成开口。