公开(公告)号：US12146873B2

公开(公告)日：2024-11-19

申请号：US17849905

申请日：2022-06-27

Applicant: IMEC VZW

Inventor： Anne Verhulst ,  Pol Van Dorpe

IPC: G01N15/06 ,  G01N15/01 ,  G01N33/487

Abstract: A method of operating a pore field-effect transistor (FET) sensor for detecting particles, wherein the pore FET sensor comprises a FET wherein a gate is controlled by a pore filled by a fluid, comprises: controlling a first voltage (Vcis) to set the FET in a subthreshold region; controlling a second voltage (Vtrans) to set a voltage difference between the first and second voltages (Vtrans) such that an effective difference in gate voltage experienced between a minimum and a maximum effective gate voltage during movement of a particle in the fluid is at least kT/q; and detecting a drain-source current in the FET, wherein the particle passing through the pore modulates the drain-source current for detecting presence of the particle.

公开(公告)号：US20240210343A1

公开(公告)日：2024-06-27

申请号：US18392429

申请日：2023-12-21

Applicant: IMEC VZW

Inventor： Anne Verhulst ,  Pol Van Dorpe ,  Liesbet Lagae ,  Cedric Huyghebaert

IPC: G01N27/12

CPC classification number: G01N27/128

Abstract: In a first aspect, a nanopore sensing device is provided that includes: (i) a nanopore having a first orifice and second orifice, and a length running from the first to the second orifice; and (ii) one or more sensors for sensing an electric feature in the nanopore; wherein the nanopore sensing device comprises a plurality of sensing layers arranged along the length, each sensing layer being part of one of the sensors and each adjacent pair of sensing layers being separated by an isolating layer, and at least one of the sensors is a field-effect transistor.

公开(公告)号：US09704992B2

公开(公告)日：2017-07-11

申请号：US15337728

申请日：2016-10-28

Applicant: IMEC VZW

Inventor： Anne Verhulst ,  Devin Verreck ,  AliReza Alian

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L29/36 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/41775 ,  H01L29/4234 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/7831

Abstract: A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.

公开(公告)号：US20170170314A1

公开(公告)日：2017-06-15

申请号：US15337728

申请日：2016-10-28

Applicant: IMEC VZW

Inventor： Anne Verhulst ,  Devin Verreck ,  AliReza Alian

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/36

CPC classification number: H01L29/7835 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/41775 ,  H01L29/4234 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/7831

Abstract: A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.