公开(公告)号：US20200176446A1

公开(公告)日：2020-06-04

申请号：US16688776

申请日：2019-11-19

Applicant: IMEC vzw

Inventor： Jacopo Franco ,  Hiroaki Arimura ,  Benjamin Kaczer

IPC: H01L27/092 ,  H01L23/367 ,  H01L21/8238 ,  H01L21/02

Abstract: A p-channel metal-oxide-semiconductor (pMOS) transistor including a gate stack which includes: a silicon oxide comprising dielectric interlayer on a substrate, wherein the dielectric interlayer has a thickness below lnm; a high-k dielectric layer having a higher dielectric constant compared to the dielectric interlayer; a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer and in direct contact with the dielectric interlayer, for shifting down a high-K bandgap of the high-k dielectric layer with relation to a valence band of the substrate, where the first dipole-forming capping layer has a thickness below 2nm; at least one work function metal above the high-k dielectric layer. Advantageously, the pMOS transistor includes low negative bias temperature instability (NBTI) and therefore high reliability without the use of a reliability anneal which makes the pMOS transistor suitable for use as back end of line (BEOL) devices.

公开(公告)号：US10469083B2

公开(公告)日：2019-11-05

申请号：US15644614

申请日：2017-07-07

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Erik Bury ,  Jacopo Franco ,  Geert Hellings ,  Robin Degraeve ,  Benjamin Kaczer

IPC: H03K19/003 ,  H01L21/326 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H04L9/14 ,  H01L23/00 ,  H04L9/08 ,  H04L9/32 ,  G09C1/00 ,  H03K17/00

Abstract: A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric.

公开(公告)号：US20220181145A1

公开(公告)日：2022-06-09

申请号：US17369709

申请日：2021-07-07

Applicant: IMEC VZW

Inventor： Jacopo Franco ,  Jean-Francois de Marneffe ,  Tibor Grasser

IPC: H01L21/02

Abstract: A method for improving a bias temperature instability of a SiO2 layer comprises exposing the SiO2 layer to atomic hydrogen.

公开(公告)号：US20180013431A1

公开(公告)日：2018-01-11

申请号：US15644614

申请日：2017-07-07

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Erik Bury ,  Jacopo Franco ,  Geert Hellings ,  Robin Degraeve ,  Benjamin Kaczer

IPC: H03K19/003 ,  H04L9/14 ,  H04L9/08 ,  H01L27/088 ,  H01L27/02 ,  H01L23/00 ,  H01L21/326 ,  H04L9/32 ,  H01L23/528 ,  H03K17/00

CPC classification number: H03K19/003 ,  G09C1/00 ,  H01L21/326 ,  H01L23/528 ,  H01L23/573 ,  H01L27/0203 ,  H01L27/088 ,  H03K17/002 ,  H04L9/0861 ,  H04L9/0866 ,  H04L9/0894 ,  H04L9/14 ,  H04L9/3278

Abstract: A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric.

公开(公告)号：US12009204B2

公开(公告)日：2024-06-11

申请号：US17369709

申请日：2021-07-07

Applicant: IMEC VZW

Inventor： Jacopo Franco ,  Jean-Francois de Marneffe ,  Tibor Grasser

IPC: H01L21/02

CPC classification number: H01L21/0234 ,  H01L21/02164

Abstract: A method for improving a bias temperature instability of a SiO2 layer comprises exposing the SiO2 layer to atomic hydrogen.

公开(公告)号：US11282837B2

公开(公告)日：2022-03-22

申请号：US16688776

申请日：2019-11-19

Applicant: IMEC vzw

Inventor： Jacopo Franco ,  Hiroaki Arimura ,  Benjamin Kaczer

IPC: H01L21/02 ,  H01L23/367 ,  H01L27/092 ,  H01L29/00 ,  H01L21/8238 ,  H01L29/51

Abstract: A p-channel metal-oxide-semiconductor (pMOS) transistor including a gate stack which includes: a silicon oxide comprising dielectric interlayer on a substrate, wherein the dielectric interlayer has a thickness below 1 nm; a high-k dielectric layer having a higher dielectric constant compared to the dielectric interlayer; a first dipole-forming capping layer between the dielectric interlayer and the high-k dielectric layer and in direct contact with the dielectric interlayer, for shifting down a high-K bandgap of the high-k dielectric layer with relation to a valence band of the substrate, where the first dipole-forming capping layer has a thickness below 2 nm; at least one work function metal above the high-k dielectric layer. Advantageously, the pMOS transistor includes low negative bias temperature instability (NBTI) and therefore high reliability without the use of a reliability anneal which makes the pMOS transistor suitable for use as back end of line (BEOL) devices.