公开(公告)号：US11380789B2

公开(公告)日：2022-07-05

申请号：US16750711

申请日：2020-01-23

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Stefaan Decoutere

IPC: H01L29/78 ,  H01L29/778 ,  H01L21/8252 ,  H01L29/20

Abstract: A vertical power device is disclosed, the device having a top side and a bottom side, and the device comprising (i) a substrate; (ii) a layered group III-Nitride based device stack formed atop the substrate; (iii) a first vertical group III-Nitride based device and a second vertical group III-Nitride based device formed in the group III-Nitride based device stack, wherein the first vertical group III-Nitride based device and the second vertical group III-Nitride based device are electrically connected; and (iv) a first vertical device isolation structure that isolates the first vertical group III-Nitride based device from the second vertical group III-Nitride based device. Also disclosed are a vertical power system integrating vertical power devices and a process for fabricating a vertical power device.

公开(公告)号：US20160163695A1

公开(公告)日：2016-06-09

申请号：US14963650

申请日：2015-12-09

Applicant: IMEC VZW

Inventor： Stefaan Decoutere ,  Niels Posthuma ,  Shuzhen You

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/761 ,  H01L21/22 ,  H01L29/778 ,  H01L21/74

CPC classification number: H01L27/0629 ,  H01L21/761 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/1075 ,  H01L29/7786

Abstract: An integrated circuit comprising a first III-N transistor having a source region and a second III-N transistor having a source region, both transistors being monolithically integrated on a common silicon substrate of a first doping type and separated from each-other by an isolation region, the substrate comprising underneath the first transistor a well of a first doping type electrically connected to the source region of the first transistor and comprising underneath the second transistor a well of a second doping type electrically connected to the source region of the second transistor, thereby forming a junction diode in the substrate between the sources of the first and the second transistor.

Abstract translation: 一种集成电路，包括具有源极区的第一III-N晶体管和具有源极区的第二III-N晶体管，两个晶体管单片集成在第一掺杂类型的公共硅衬底上并且通过隔离彼此分离 所述衬底包括在所述第一晶体管下方的第一掺杂类型的阱，所述阱的第一掺杂类型电连接到所述第一晶体管的源极区，并且在所述第二晶体管的下方包括电连接到所述第二晶体管的源极区的第二掺杂型阱， 从而在第一和第二晶体管的源极之间的衬底中形成结二极管。

公开(公告)号：US11094629B2

公开(公告)日：2021-08-17

申请号：US16726120

申请日：2019-12-23

Applicant: IMEC VZW

Inventor： Stefaan Decoutere ,  Steve Stoffels

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/64 ,  H01L29/20 ,  H01L21/8258 ,  H01L27/06 ,  H01L23/367 ,  H01L23/528

Abstract: A three-dimensional (3D) power device having a plurality of layers that are stacked on top of each other and insulated from each other by interlayers, the plurality of layers comprising a lower layer comprising electrical and thermal conductors; a group III-Nitride based device layer formed above the lower layer, the group III-Nitride based device layer comprising at least one group III-Nitride based power device; a control layer formed above the group III-Nitride based device layer, the control layer comprising at least one control device; and a redistribution layer in between the group III-Nitride based device layer and the control layer, the current redistribution layer comprising a metal pattern being provided for laterally redistributing electrical currents and/or heat.

公开(公告)号：US20200243678A1

公开(公告)日：2020-07-30

申请号：US16750711

申请日：2020-01-23

Applicant: IMEC VZW

Inventor： Steve Stoffels ,  Stefaan Decoutere

IPC: H01L29/78 ,  H01L21/8252 ,  H01L29/778

Abstract: A vertical power device is disclosed, the device having a top side and a bottom side, and the device comprising (i) a substrate; (ii) a layered group III-Nitride based device stack formed atop the substrate; (iii) a first vertical group III-Nitride based device and a second vertical group III-Nitride based device formed in the group III-Nitride based device stack, wherein the first vertical group III-Nitride based device and the second vertical group III-Nitride based device are electrically connected; and (iv) a first vertical device isolation structure that isolates the first vertical group III-Nitride based device from the second vertical group III-Nitride based device. Also disclosed are a vertical power system integrating vertical power devices and a process for fabricating a vertical power device.

公开(公告)号：US12002680B2

公开(公告)日：2024-06-04

申请号：US17345229

申请日：2021-06-11

Applicant: IMEC VZW

Inventor： Niels Posthuma ,  Stefaan Decoutere

IPC: H01L21/285 ,  H01L21/3213 ,  H01L29/20 ,  H01L29/423 ,  H01L29/47 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/28581 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method includes providing a semiconductor structure including: a substrate; a layer stack with each layer of the layer stack including a Group III-nitride material; and a p-type doped GaN layer on the layer stack. The method also includes providing, on the GaN layer, a metal bi-layer including a first metal layer in contact with GaN layer and a second metal layer on the first metal layer and having a lower sheet resistance than the first metal layer. The method also includes performing a patterning process upon the metal bi-layer and the p-type doped GaN layer such that a first periphery of the first metal layer is aligned to a second periphery of the second metal layer and such that a first cross section of the metal bi-layer is smaller than a second cross section of the GaN layer parallel to the first cross section.

公开(公告)号：US20220181159A1

公开(公告)日：2022-06-09

申请号：US17345229

申请日：2021-06-11

Applicant: IMEC VZW

Inventor： Niels Posthuma ,  Stefaan Decoutere

IPC: H01L21/285 ,  H01L29/20 ,  H01L29/423 ,  H01L29/47 ,  H01L29/778 ,  H01L21/3213 ,  H01L29/66

Abstract: A method includes providing a semiconductor structure including: a substrate; a layer stack with each layer of the layer stack including a Group III-nitride material; and a p-type doped GaN layer on the layer stack. The method also includes providing, on the GaN layer, a metal bi-layer including a first metal layer in contact with GaN layer and a second metal layer on the first metal layer and having a lower sheet resistance than the first metal layer. The method also includes performing a patterning process upon the metal bi-layer and the p-type doped GaN layer such that a first periphery of the first metal layer is aligned to a second periphery of the second metal layer and such that a first cross section of the metal bi-layer is smaller than a second cross section of the GaN layer parallel to the first cross section.