公开(公告)号：US10469083B2

公开(公告)日：2019-11-05

申请号：US15644614

申请日：2017-07-07

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Erik Bury ,  Jacopo Franco ,  Geert Hellings ,  Robin Degraeve ,  Benjamin Kaczer

IPC: H03K19/003 ,  H01L21/326 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H04L9/14 ,  H01L23/00 ,  H04L9/08 ,  H04L9/32 ,  G09C1/00 ,  H03K17/00

Abstract: A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric.

公开(公告)号：US20180046899A1

公开(公告)日：2018-02-15

申请号：US15650749

申请日：2017-07-14

Applicant: IMEC VZW

Inventor： Robin Degraeve ,  Dimitrios Rodopoulos

IPC: G06N3/04 ,  G06N3/08 ,  G06F12/02

CPC classification number: G06N3/049 ,  G06F12/0207 ,  G06F2212/1016 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/0472 ,  G06N3/0635 ,  G06N3/08

Abstract: A hardware implementation of a temporal memory system is disclosed. One aspect includes at least one array of memory cells logically organized in rows and columns, wherein each of the memory cells is adapted for storing a scalar value and adapted for changing the stored scalar value. The hardware implementation additionally includes an input system adapted for receiving an input frame as input and for creating a representation for the input, where the input comprises information for addressing the memory cells in the at least one array. The hardware implantation additionally includes at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address. The at least one addressing unit includes a column addressing unit for receiving the representation or a derivative thereof as input and applying the representation or the derivative as a column address to the array of memory cells, and a row addressing unit for receiving a delayed version of the representation at a specified time in the past as input, and applying this representation as a row address to the array of cells. The hardware implementation further includes a reading unit adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied, wherein each scalar values read out by the reading unit corresponds to a likelihood of temporal coincidence between the input representation of the row address and the input representation of the column address, the likelihood being adjustable through the scalar value stored in the memory cell.

公开(公告)号：US10680597B2

公开(公告)日：2020-06-09

申请号：US16414609

申请日：2019-05-16

Applicant: IMEC vzw

Inventor： Daniele Garbin ,  Robin Degraeve ,  Ludovic Goux

IPC: H03K17/0412 ,  H01L45/00

Abstract: The disclosed technology generally relates to a switching device and more particularly to a switching device based on an active portion capable of switching from an insulating state to a conductive state. In an aspect, a switching device comprises an active portion interposed between two electrodes and capable of switching from an insulating state to a conducting state when a voltage higher than a threshold value is applied between the two electrodes. The threshold value is lowered by a dielectric permittivity distribution which produces a concentration of electrical field at a location within the active portion. Thus, the switching device may be devoid of a third control electrode.

公开(公告)号：US20190356308A1

公开(公告)日：2019-11-21

申请号：US16414609

申请日：2019-05-16

Applicant: IMEC vzw

Inventor： Daniele Garbin ,  Robin Degraeve ,  Ludovic Goux

IPC: H03K17/0412 ,  H01L45/00

Abstract: The disclosed technology generally relates to a switching device and more particularly to a switching device based on an active portion capable of switching from an insulating state to a conductive state. In an aspect, a switching device comprises an active portion interposed between two electrodes and capable of switching from an insulating state to a conducting state when a voltage higher than a threshold value is applied between the two electrodes. The threshold value is lowered by a dielectric permittivity distribution which produces a concentration of electrical field at a location within the active portion. Thus, the switching device may be devoid of a third control electrode.

公开(公告)号：US10452972B2

公开(公告)日：2019-10-22

申请号：US15650749

申请日：2017-07-14

Applicant: IMEC VZW

Inventor： Robin Degraeve ,  Dimitrios Rodopoulos

IPC: G06F12/02 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063

Abstract: A hardware implementation of a temporal memory system is disclosed. One aspect includes at least one array of memory cells logically organized in rows and columns, wherein each of the memory cells is adapted for storing a scalar value and adapted for changing the stored scalar value. The hardware implementation additionally includes an input system adapted for receiving an input frame as input and for creating a representation for the input, where the input comprises information for addressing the memory cells in the at least one array. The hardware implantation additionally includes at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address. The at least one addressing unit includes a column addressing unit for receiving the representation or a derivative thereof as input and applying the representation or the derivative as a column address to the array of memory cells, and a row addressing unit for receiving a delayed version of the representation at a specified time in the past as input, and applying this representation as a row address to the array of cells. The hardware implementation further includes a reading unit adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied, wherein each scalar values read out by the reading unit corresponds to a likelihood of temporal coincidence between the input representation of the row address and the input representation of the column address, the likelihood being adjustable through the scalar value stored in the memory cell.

公开(公告)号：US20180013431A1

公开(公告)日：2018-01-11

申请号：US15644614

申请日：2017-07-07

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Erik Bury ,  Jacopo Franco ,  Geert Hellings ,  Robin Degraeve ,  Benjamin Kaczer

IPC: H03K19/003 ,  H04L9/14 ,  H04L9/08 ,  H01L27/088 ,  H01L27/02 ,  H01L23/00 ,  H01L21/326 ,  H04L9/32 ,  H01L23/528 ,  H03K17/00

CPC classification number: H03K19/003 ,  G09C1/00 ,  H01L21/326 ,  H01L23/528 ,  H01L23/573 ,  H01L27/0203 ,  H01L27/088 ,  H03K17/002 ,  H04L9/0861 ,  H04L9/0866 ,  H04L9/0894 ,  H04L9/14 ,  H04L9/3278

Abstract: A device and a method for implementing a physically unclonable function is disclosed. In one aspect, the device includes at least one electronic structure including a dielectric. A conductive path is formed at a random position through the dielectric due to an electrical breakdown of the dielectric, or the electronic structure is adapted for generating an electrical breakdown of the dielectric such that the conductive path is formed through the dielectric at a random position. The at least one electronic structure is adapted for determining a distinct value of a set comprising at least two predetermined values. The distinct value is determined by the position of the conductive path through the dielectric.