公开(公告)号：US20190034111A1

公开(公告)日：2019-01-31

申请号：US16028328

申请日：2018-07-05

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Francky Catthoor ,  Praveen Raghavan ,  Daniele Garbin ,  Dimitrios Rodopoulos ,  Odysseas Zografos

IPC: G06F3/06 ,  G06N3/08

CPC classification number: G06F3/0646 ,  G06F3/0604 ,  G06F3/0673 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  G06N3/088 ,  G11C7/1006 ,  G11C11/54 ,  G11C13/0002 ,  G11C13/0061 ,  G11C16/04 ,  G11C17/165 ,  G11C2213/71

Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.

公开(公告)号：US11443174B2

公开(公告)日：2022-09-13

申请号：US16682466

申请日：2019-11-13

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Daniele Garbin ,  Simone Lavizzari

IPC: G06N3/063 ,  G11C13/00 ,  G11C16/26

Abstract: A neural network circuit for providing a threshold weighted sum of input signals comprises at least two arrays of transistors with programmable threshold voltage, each transistor storing a synaptic weight as a threshold voltage and having a control electrode for receiving an activation input signal. Additionally, for each array of transistors, a reference network associated therewith, which provides a reference signal to be combined with the positive or negative weight current components of the transistors of the associated array, the reference signal having opposite sign compared to the weight current components of the associated array, thereby providing the threshold of the weighted sums of the currents. Further, at least one bitline is configured to receive the combined positive and/or negative current components, each combined with their associated reference signals.

公开(公告)号：US20180144240A1

公开(公告)日：2018-05-24

申请号：US15820239

申请日：2017-11-21

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Daniele Garbin ,  Dimitrios Rodopoulos ,  Peter Debacker ,  Praveen Raghavan

IPC: G06N3/063 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06N3/04 ,  G06N3/0454 ,  G11C11/1659 ,  G11C11/54 ,  G11C13/003 ,  G11C2213/79 ,  H03K19/168

Abstract: The disclosed technology generally relates to machine learning, and more particularly to integration of basic machine learning kernels in a semiconductor device. In an aspect, a semiconductor cell is configured to perform one or more logic operations such as one or both of an XNOR and an XOR operation. The semiconductor cell includes a memory unit configured to store a first operand, an input port unit configured to receive a second operand and a switch unit configured to implement one or more logic operations on the stored first operand and the received second operand. The semiconductor cell additionally includes a readout port configured to provide an output of one or more logic operations. A plurality of cells may be organized in an array, and one or more of such arrays may be used to implement a neural network.

公开(公告)号：US10802743B2

公开(公告)日：2020-10-13

申请号：US16028328

申请日：2018-07-05

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Francky Catthoor ,  Praveen Raghavan ,  Daniele Garbin ,  Dimitrios Rodopoulos ,  Odysseas Zografos

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/04 ,  G11C13/00 ,  G11C7/10 ,  G06N3/063 ,  G11C17/16 ,  G11C11/54 ,  G06N3/04 ,  G06N3/08

Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.

公开(公告)号：US10680597B2

公开(公告)日：2020-06-09

申请号：US16414609

申请日：2019-05-16

Applicant: IMEC vzw

Inventor： Daniele Garbin ,  Robin Degraeve ,  Ludovic Goux

IPC: H03K17/0412 ,  H01L45/00

Abstract: The disclosed technology generally relates to a switching device and more particularly to a switching device based on an active portion capable of switching from an insulating state to a conductive state. In an aspect, a switching device comprises an active portion interposed between two electrodes and capable of switching from an insulating state to a conducting state when a voltage higher than a threshold value is applied between the two electrodes. The threshold value is lowered by a dielectric permittivity distribution which produces a concentration of electrical field at a location within the active portion. Thus, the switching device may be devoid of a third control electrode.

公开(公告)号：US20200151550A1

公开(公告)日：2020-05-14

申请号：US16682466

申请日：2019-11-13

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Daniele Garbin ,  Simone Lavizzari

IPC: G06N3/063 ,  G11C13/00

Abstract: A neural network circuit for providing a threshold weighted sum of input signals comprises at least two arrays of transistors with programmable threshold voltage, each transistor storing a synaptic weight as a threshold voltage and having a control electrode for receiving an activation input signal. Additionally, for each array of transistors, a reference network associated therewith, which provides a reference signal to be combined with the positive or negative weight current components of the transistors of the associated array, the reference signal having opposite sign compared to the weight current components of the associated array, thereby providing the threshold of the weighted sums of the currents. Further, at least one bitline is configured to receive the combined positive and/or negative current components, each combined with their associated reference signals.

公开(公告)号：US20190356308A1

公开(公告)日：2019-11-21

申请号：US16414609

申请日：2019-05-16

Applicant: IMEC vzw

Inventor： Daniele Garbin ,  Robin Degraeve ,  Ludovic Goux

IPC: H03K17/0412 ,  H01L45/00

Abstract: The disclosed technology generally relates to a switching device and more particularly to a switching device based on an active portion capable of switching from an insulating state to a conductive state. In an aspect, a switching device comprises an active portion interposed between two electrodes and capable of switching from an insulating state to a conducting state when a voltage higher than a threshold value is applied between the two electrodes. The threshold value is lowered by a dielectric permittivity distribution which produces a concentration of electrical field at a location within the active portion. Thus, the switching device may be devoid of a third control electrode.