公开(公告)号：US20190034111A1

公开(公告)日：2019-01-31

申请号：US16028328

申请日：2018-07-05

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Francky Catthoor ,  Praveen Raghavan ,  Daniele Garbin ,  Dimitrios Rodopoulos ,  Odysseas Zografos

IPC: G06F3/06 ,  G06N3/08

CPC classification number: G06F3/0646 ,  G06F3/0604 ,  G06F3/0673 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  G06N3/088 ,  G11C7/1006 ,  G11C11/54 ,  G11C13/0002 ,  G11C13/0061 ,  G11C16/04 ,  G11C17/165 ,  G11C2213/71

Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.

公开(公告)号：US20180144240A1

公开(公告)日：2018-05-24

申请号：US15820239

申请日：2017-11-21

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Daniele Garbin ,  Dimitrios Rodopoulos ,  Peter Debacker ,  Praveen Raghavan

IPC: G06N3/063 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06N3/04 ,  G06N3/0454 ,  G11C11/1659 ,  G11C11/54 ,  G11C13/003 ,  G11C2213/79 ,  H03K19/168

Abstract: The disclosed technology generally relates to machine learning, and more particularly to integration of basic machine learning kernels in a semiconductor device. In an aspect, a semiconductor cell is configured to perform one or more logic operations such as one or both of an XNOR and an XOR operation. The semiconductor cell includes a memory unit configured to store a first operand, an input port unit configured to receive a second operand and a switch unit configured to implement one or more logic operations on the stored first operand and the received second operand. The semiconductor cell additionally includes a readout port configured to provide an output of one or more logic operations. A plurality of cells may be organized in an array, and one or more of such arrays may be used to implement a neural network.

公开(公告)号：US20180046899A1

公开(公告)日：2018-02-15

申请号：US15650749

申请日：2017-07-14

Applicant: IMEC VZW

Inventor： Robin Degraeve ,  Dimitrios Rodopoulos

IPC: G06N3/04 ,  G06N3/08 ,  G06F12/02

CPC classification number: G06N3/049 ,  G06F12/0207 ,  G06F2212/1016 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/0472 ,  G06N3/0635 ,  G06N3/08

Abstract: A hardware implementation of a temporal memory system is disclosed. One aspect includes at least one array of memory cells logically organized in rows and columns, wherein each of the memory cells is adapted for storing a scalar value and adapted for changing the stored scalar value. The hardware implementation additionally includes an input system adapted for receiving an input frame as input and for creating a representation for the input, where the input comprises information for addressing the memory cells in the at least one array. The hardware implantation additionally includes at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address. The at least one addressing unit includes a column addressing unit for receiving the representation or a derivative thereof as input and applying the representation or the derivative as a column address to the array of memory cells, and a row addressing unit for receiving a delayed version of the representation at a specified time in the past as input, and applying this representation as a row address to the array of cells. The hardware implementation further includes a reading unit adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied, wherein each scalar values read out by the reading unit corresponds to a likelihood of temporal coincidence between the input representation of the row address and the input representation of the column address, the likelihood being adjustable through the scalar value stored in the memory cell.

公开(公告)号：US20200159809A1

公开(公告)日：2020-05-21

申请号：US16685892

申请日：2019-11-15

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Praveen Raghavan ,  Dimitrios Rodopoulos ,  Mohit Dandekar

IPC: G06F17/15 ,  G06N3/04 ,  G06N3/08

Abstract: A method and hardware system for mapping an input map of a convolutional neural network layer to an output map are disclosed. An array of processing elements are interconnected to support unidirectional dataflows through the array along at least three different spatial directions. Each processing element is adapted to combine values of dataflows along different spatial directions into a new value for at least one of the supported dataflows. For each data entry in the output map, a plurality of products from pairs of weights of a selected convolution kernel and selected data entries in the input map is provided and arranged into a plurality of associated partial sums. Products associated with a same partial sum are accumulated on the array and accumulated on the array into at least one data entry in the output map.

公开(公告)号：US11704462B2

公开(公告)日：2023-07-18

申请号：US16522555

申请日：2019-07-25

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Pieter Weckx ,  Dimitrios Rodopoulos ,  Benjamin Kaczer ,  Francky Catthoor

IPC: G06F30/367

CPC classification number: G06F30/367

Abstract: A system and method for simulating an electronic circuit is disclosed. The method includes creating a finite set of circuit or device parameter points selected from within an n-dimensional parameter space. The method includes determining, for each circuit or device parameter point of the set, a corresponding response value of the performance metric and a corresponding probability of occurrence. The method includes determining, for a predetermined value of the performance metric, the total probability of occurrence.

公开(公告)号：US11475101B2

公开(公告)日：2022-10-18

申请号：US16685892

申请日：2019-11-15

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Praveen Raghavan ,  Dimitrios Rodopoulos ,  Mohit Dandekar

IPC: G06F17/15 ,  G06N3/04 ,  G06N3/08

Abstract: A method and hardware system for mapping an input map of a convolutional neural network layer to an output map are disclosed. An array of processing elements are interconnected to support unidirectional dataflows through the array along at least three different spatial directions. Each processing element is adapted to combine values of dataflows along different spatial directions into a new value for at least one of the supported dataflows. For each data entry in the output map, a plurality of products from pairs of weights of a selected convolution kernel and selected data entries in the input map is provided and arranged into a plurality of associated partial sums. Products associated with a same partial sum are accumulated on the array and accumulated on the array into at least one data entry in the output map.

公开(公告)号：US10802743B2

公开(公告)日：2020-10-13

申请号：US16028328

申请日：2018-07-05

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Francky Catthoor ,  Praveen Raghavan ,  Daniele Garbin ,  Dimitrios Rodopoulos ,  Odysseas Zografos

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/04 ,  G11C13/00 ,  G11C7/10 ,  G06N3/063 ,  G11C17/16 ,  G11C11/54 ,  G06N3/04 ,  G06N3/08

Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.

公开(公告)号：US10452972B2

公开(公告)日：2019-10-22

申请号：US15650749

申请日：2017-07-14

Applicant: IMEC VZW

Inventor： Robin Degraeve ,  Dimitrios Rodopoulos

IPC: G06F12/02 ,  G06N3/04 ,  G06N3/08 ,  G06N3/063

Abstract: A hardware implementation of a temporal memory system is disclosed. One aspect includes at least one array of memory cells logically organized in rows and columns, wherein each of the memory cells is adapted for storing a scalar value and adapted for changing the stored scalar value. The hardware implementation additionally includes an input system adapted for receiving an input frame as input and for creating a representation for the input, where the input comprises information for addressing the memory cells in the at least one array. The hardware implantation additionally includes at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address. The at least one addressing unit includes a column addressing unit for receiving the representation or a derivative thereof as input and applying the representation or the derivative as a column address to the array of memory cells, and a row addressing unit for receiving a delayed version of the representation at a specified time in the past as input, and applying this representation as a row address to the array of cells. The hardware implementation further includes a reading unit adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied, wherein each scalar values read out by the reading unit corresponds to a likelihood of temporal coincidence between the input representation of the row address and the input representation of the column address, the likelihood being adjustable through the scalar value stored in the memory cell.