公开(公告)号：US20250005159A1

公开(公告)日：2025-01-02

申请号：US18217484

申请日：2023-06-30

Applicant: INTEL CORPORATION

Inventor： Avinash CHANDRASEKARAN ,  Murugasamy K. NACHIMUTHU ,  Mariusz ORIOL ,  Piotr MATUSZCZAK

IPC: G06F21/57 ,  G06F8/65 ,  G06F21/44

Abstract: An apparatus and method are described for staging and activating microcode of a processor. For example, one embodiment of a processor comprises: a plurality of functional blocks, each functional block operable, at least in part, based on microcode and including a non-volatile memory to store a corresponding microcode update (MCU); a plurality of MCU staging memories, each MCU staging memory to temporarily store one or more of the MCUs for one or more corresponding functional blocks of the plurality of functional blocks; authentication hardware logic to attempt to validate each MCU of the one or more MCUs stored in each MCU staging memory, wherein each MCU is to be copied to a non-volatile memory of a corresponding functional block only after a successful authentication.

公开(公告)号：US20240160431A1

公开(公告)日：2024-05-16

申请号：US18391637

申请日：2023-12-20

Applicant: Intel Corporation

Inventor： Mohan J. KUMAR ,  Murugasamy K. NACHIMUTHU ,  Daniel K. OSAWA ,  Maciej PLUCINSKI ,  Avinash CHANDRASEKARAN

IPC: G06F8/65 ,  G06F9/4401

CPC classification number: G06F8/65 ,  G06F9/4401

Abstract: Examples described herein relate to updating boot firmware code or microcode. In some examples, a management controller includes a memory and a system processor, coupled to the management controller, is to: based on a first configuration, perform a boot operation by a read of first boot firmware code from the memory of the management controller. Based on a second configuration, the system processor is to perform a boot operation by a read of second boot firmware code from a flash memory.