公开(公告)号：US20230083193A1

公开(公告)日：2023-03-16

申请号：US17348435

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Shen ZHOU ,  Xiaoming DU ,  Cong LI ,  Kuljit S. BAINS ,  Rajat AGARWAL ,  Murugasamy K. NACHIMUTHU ,  Maciej LAWNICZAK ,  Chao Yan TANG ,  Mariusz ORIOL

IPC: G06F11/07

Abstract: A system can predict memory device failure through identification of correctable error patterns based on the memory architecture. The failure prediction can thus account for the circuit-level of the memory rather than the mere number or frequency of correctable errors. A failure prediction engine correlates hardware configuration of the memory device with correctable errors (CEs) detected in data of the memory device to predict an uncorrectable error (UE) based on the correlation.

公开(公告)号：US20210255915A1

公开(公告)日：2021-08-19

申请号：US17246388

申请日：2021-04-30

Applicant: Intel Corporation

Inventor： Mohan J. KUMAR ,  Murugasamy K. NACHIMUTHU ,  Krishna Bhuyan

IPC: G06F11/07 ,  G06F11/30 ,  H05K7/14

Abstract: Technologies for composing a managed node with multiple processors on multiple compute sleds to cooperatively execute a workload include a memory, one or more processors connected to the memory, and an accelerator. The accelerator further includes a coherence logic unit that is configured to receive a node configuration request to execute a workload. The node configuration request identifies the compute sled and a second compute sled to be included in a managed node. The coherence logic unit is further configured to modify a portion of local working data associated with the workload on the compute sled in the memory with the one or more processors of the compute sled, determine coherence data indicative of the modification made by the one or more processors of the compute sled to the local working data in the memory, and send the coherence data to the second compute sled of the managed node.

公开(公告)号：US20180143678A1

公开(公告)日：2018-05-24

申请号：US15823527

申请日：2017-11-27

Applicant: Intel Corporation

Inventor： Mohan J. KUMAR ,  Murugasamy K. NACHIMUTHU

IPC: G06F1/32 ,  G06F9/4401

CPC classification number: G06F1/3206 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/4418 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to enhance support to sleep states. The computer system includes a processor, a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable, and power management (PM) module. A dynamic random access memory (DRAM) provides a portion of system address space. The PM module intercepts a request initiated by an operating system for entry into a sleep state, copies data from the DRAM to the NVRAM, maps the portion of the system address space from the DRAM to the NVRAM, and turns off the DRAM when transitioning into the sleep state. Upon occurrence of a wake event, the PM module returns control to the operating system such that the computer system resumes working state operations without the operating system knowing that the portion of the system address space has been mapped to the NVRAM.

公开(公告)号：US20210208869A1

公开(公告)日：2021-07-08

申请号：US17210240

申请日：2021-03-23

Applicant: Intel Corporation

Inventor： Murugasamy K. NACHIMUTHU ,  Ruixia LI ,  Siyuan FU ,  Jiewen YAO ,  Wei XU

IPC: G06F8/656 ,  G06F9/445 ,  G06F13/16

Abstract: System, method, and instructions for providing system management mode (SMM) runtime telemetry support. An SMM Telemetry Service component is responsible for collecting telemetry information from other SMM components, as well as exposing the information to non-firmware component on request. The SMM Telemetry Service collects telemetry information produced by an SMM Runtime Update handler and other SMM drivers and exposes the telemetry information at runtime to an upper layer OS consumer or management unit (e.g., BMC, CSME, etc.). Since the SMM Telemetry Service is a standalone module and independent of other SMM service(s), the service is available even during a runtime SMM Driver Update. The embodiments also disclose a mechanism for managing a shared telemetry data region that can be accessed by the data producer (SMM components) and consumer (non-SMM components), without introducing additional SMI that affects system performance.

公开(公告)号：US20200326925A1

公开(公告)日：2020-10-15

申请号：US16913819

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Murugasamy K. NACHIMUTHU ,  Mohan J. KUMAR ,  Tiffany J. KASANICKY ,  Christopher HESS ,  Sarathy JAYAKUMAR ,  Daniel K. OSAWA ,  Maciej PLUCINSKI ,  Krzysztof RUSOCKI ,  Jason M. BILLS

IPC: G06F8/65

Abstract: Examples include updating firmware for a persistent memory module in a computing system during runtime. Examples include downloading firmware to the persistent memory module; saving settings of one or more input/output (I/O) devices of the computing system and setting a timeout value of the one or more I/O devices to greater than a time to activate the firmware in the persistent memory module. Examples include updating the firmware in the persistent memory module during runtime of the computing system by quiescing access to one or more memory modules of the computing system; sending a request to the persistent memory module to activate the firmware; waiting for the request to activate the firmware to be completed by the persistent memory module; and un-quiescing access to the one or more memory modules of the computing system; and restoring the saved settings for the one or more I/O devices.

公开(公告)号：US20200050497A1

公开(公告)日：2020-02-13

申请号：US16344582

申请日：2017-11-29

Applicant: INTEL CORPORATION

Inventor： Mohan J. KUMAR ,  Murugasamy K. NACHIMUTHU ,  Krishna BHUYAN

IPC: G06F9/50

Abstract: Technologies for composing a managed node with multiple processors on multiple compute sleds to cooperatively execute a workload include a memory, one or more processors connected to the memory, and an accelerator. The accelerator further includes a coherence logic unit that is configured to receive a node configuration request to execute a workload. The node configuration request identifies the compute sled and a second compute sled to be included in a managed node. The coherence logic unit is further configured to modify a portion of local working data associated with the workload on the compute sled in the memory with the one or more processors of the compute sled, determine coherence data indicative of the modification made by the one or more processors of the compute sled to the local working data in the memory, and send the coherence data to the second compute sled of the managed node.

公开(公告)号：US20180032429A1

公开(公告)日：2018-02-01

申请号：US15224134

申请日：2016-07-29

Applicant: Intel Corporation

Inventor： Min LIU ,  Zhenlin LUO ,  George VERGIS ,  Murugasamy K. NACHIMUTHU ,  Mohan J. KUMAR ,  Ross E. ZWISLER

IPC: G06F12/02 ,  G06F12/0873 ,  G06F12/0871 ,  G06F12/084 ,  G06F12/0842

CPC classification number: G06F12/023 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0871 ,  G06F12/0873 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/202 ,  G06F2212/205 ,  G06F2212/222 ,  G06F2212/225 ,  G06F2212/271 ,  G06F2212/305 ,  G06F2212/604

Abstract: A method is described. The method includes recognizing different latencies and/or bandwidths between different levels of a system memory and different memory access requestors of a computing system. The system memory includes the different levels and different technologies. The method also includes allocating each of the memory access requestors with a respective region of the system memory having an appropriate latency and/or bandwidth.

公开(公告)号：US20250005159A1

公开(公告)日：2025-01-02

申请号：US18217484

申请日：2023-06-30

Applicant: INTEL CORPORATION

Inventor： Avinash CHANDRASEKARAN ,  Murugasamy K. NACHIMUTHU ,  Mariusz ORIOL ,  Piotr MATUSZCZAK

IPC: G06F21/57 ,  G06F8/65 ,  G06F21/44

Abstract: An apparatus and method are described for staging and activating microcode of a processor. For example, one embodiment of a processor comprises: a plurality of functional blocks, each functional block operable, at least in part, based on microcode and including a non-volatile memory to store a corresponding microcode update (MCU); a plurality of MCU staging memories, each MCU staging memory to temporarily store one or more of the MCUs for one or more corresponding functional blocks of the plurality of functional blocks; authentication hardware logic to attempt to validate each MCU of the one or more MCUs stored in each MCU staging memory, wherein each MCU is to be copied to a non-volatile memory of a corresponding functional block only after a successful authentication.

公开(公告)号：US20210011706A1

公开(公告)日：2021-01-14

申请号：US17031012

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Murugasamy K. NACHIMUTHU ,  Mohan J. KUMAR ,  Muthukumar P. SWAMINATHAN ,  Daniel K. OSAWA ,  Maciej PLUCINSKI

IPC: G06F8/65 ,  G06F21/44 ,  G06F3/06

Abstract: Examples include updating firmware for a persistent memory module in a computing system during runtime. Examples include copying a new version of persistent memory module firmware into an available area of random-access memory (RAM) in the persistent memory module, and transferring processing of a current version of persistent memory module firmware to the new version of persistent memory module firmware during runtime of the computing system, without a reset of the computing system and without quiesce of access to persistent memory media in the persistent memory module, while continuing to perform critical event handling by the current version of persistent memory module firmware. Examples further include initializing the new version of persistent memory module firmware; and transferring processing of critical event handling from the current version of persistent memory module firmware to the new version of persistent memory module firmware when initializing the new version of persistent memory module firmware is completed.

公开(公告)号：US20190042144A1

公开(公告)日：2019-02-07

申请号：US16109606

申请日：2018-08-22

Applicant: Intel Corporation

Inventor： Scott D. PETERSON ,  Sujoy SEN ,  Anjaneya R. CHAGAM REDDY ,  Murugasamy K. NACHIMUTHU ,  Mohan J. KUMAR

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/067 ,  G06F3/0679

Abstract: Examples include methods for obtaining one or more location hints applicable to a range of logical block addresses of a received input/output (I/O) request for a storage subsystem coupled with a host system over a non-volatile memory express over fabric (NVMe-oF) interconnect. The following steps are performed for each logical block address in the I/O request. A most specific location hint of the one or more location hints that matches that logical block address is applied to identify a destination in the storage subsystem for the I/O request. When the most specific location hint is a consistent hash hint, the consistent hash hint is processed. The I/O request is forwarded to the destination and a completion status for the I/O request is returned. When a location hint log page has changed, the location hint log page is processed. When any location hint refers to NVMe-oF qualified names not included in the immediately preceding query by the discovery service, the immediately preceding query is processed again.