公开(公告)号：US20210011706A1

公开(公告)日：2021-01-14

申请号：US17031012

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Murugasamy K. NACHIMUTHU ,  Mohan J. KUMAR ,  Muthukumar P. SWAMINATHAN ,  Daniel K. OSAWA ,  Maciej PLUCINSKI

IPC: G06F8/65 ,  G06F21/44 ,  G06F3/06

Abstract: Examples include updating firmware for a persistent memory module in a computing system during runtime. Examples include copying a new version of persistent memory module firmware into an available area of random-access memory (RAM) in the persistent memory module, and transferring processing of a current version of persistent memory module firmware to the new version of persistent memory module firmware during runtime of the computing system, without a reset of the computing system and without quiesce of access to persistent memory media in the persistent memory module, while continuing to perform critical event handling by the current version of persistent memory module firmware. Examples further include initializing the new version of persistent memory module firmware; and transferring processing of critical event handling from the current version of persistent memory module firmware to the new version of persistent memory module firmware when initializing the new version of persistent memory module firmware is completed.

公开(公告)号：US20190042144A1

公开(公告)日：2019-02-07

申请号：US16109606

申请日：2018-08-22

Applicant: Intel Corporation

Inventor： Scott D. PETERSON ,  Sujoy SEN ,  Anjaneya R. CHAGAM REDDY ,  Murugasamy K. NACHIMUTHU ,  Mohan J. KUMAR

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/067 ,  G06F3/0679

Abstract: Examples include methods for obtaining one or more location hints applicable to a range of logical block addresses of a received input/output (I/O) request for a storage subsystem coupled with a host system over a non-volatile memory express over fabric (NVMe-oF) interconnect. The following steps are performed for each logical block address in the I/O request. A most specific location hint of the one or more location hints that matches that logical block address is applied to identify a destination in the storage subsystem for the I/O request. When the most specific location hint is a consistent hash hint, the consistent hash hint is processed. The I/O request is forwarded to the destination and a completion status for the I/O request is returned. When a location hint log page has changed, the location hint log page is processed. When any location hint refers to NVMe-oF qualified names not included in the immediately preceding query by the discovery service, the immediately preceding query is processed again.

公开(公告)号：US20170249250A1

公开(公告)日：2017-08-31

申请号：US15457847

申请日：2017-03-13

Applicant: Intel Corporation

Inventor： Raj K. RAMANUJAN ,  Rajat AGARWAL ,  Kai CHENG ,  Taarinya POLEPEDDI ,  Camille C. RAAD ,  David J. ZIMMERMAN ,  Muthukumar P. SWAMINATHAN ,  Dimitrios ZIAKAS ,  Mohan J. KUMAR ,  Bassam N. COURY ,  Glenn J. HINTON

IPC: G06F12/0811 ,  G11C11/406 ,  G06F12/0895 ,  G06F12/0897 ,  G11C14/00

CPC classification number: G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/2024 ,  G06F2212/205 ,  G11C11/40615 ,  G11C14/009 ,  Y02D10/13

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

公开(公告)号：US20170206010A1

公开(公告)日：2017-07-20

申请号：US15477857

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Murugasamy K. NACHIMUTHU ,  Mohan J. KUMAR

IPC: G06F3/06 ,  G06F12/0888

CPC classification number: G06F1/3275 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0647 ,  G06F3/0685 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0888 ,  G06F12/1027 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/60 ,  Y02D10/13 ,  Y02D10/14

Abstract: A method is described that includes deciding to enter a lower power state, and, shutting down a memory channel in a computer system in response where thereafter other memory channels in the computer system remain active so that computer remains operative while the memory channel is shutdown.

公开(公告)号：US20220374320A1

公开(公告)日：2022-11-24

申请号：US17854449

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Chuan SONG ,  Mohan J. KUMAR ,  Feng JIANG ,  Yang ZHANG ,  Chong HAN

IPC: G06F11/20

Abstract: Examples described herein relate to execution of multiple Reliability Availability Serviceability (RAS) processes on different processors of the at least two processors to provide fallback from a first RAS process to a second RAS process executing on a processor of the at least two processors based on failure or timeout of the first RAS process. In some examples, the different processors comprise independently operating processors whereby failure or inoperability of one of the different processors is independent of another of the different processors. In some examples, failure or timeout of the first RAS process comprises failure of the second RAS process to receive an operating status signal from the first RAS process.

公开(公告)号：US20210255915A1

公开(公告)日：2021-08-19

申请号：US17246388

申请日：2021-04-30

Applicant: Intel Corporation

Inventor： Mohan J. KUMAR ,  Murugasamy K. NACHIMUTHU ,  Krishna Bhuyan

IPC: G06F11/07 ,  G06F11/30 ,  H05K7/14

Abstract: Technologies for composing a managed node with multiple processors on multiple compute sleds to cooperatively execute a workload include a memory, one or more processors connected to the memory, and an accelerator. The accelerator further includes a coherence logic unit that is configured to receive a node configuration request to execute a workload. The node configuration request identifies the compute sled and a second compute sled to be included in a managed node. The coherence logic unit is further configured to modify a portion of local working data associated with the workload on the compute sled in the memory with the one or more processors of the compute sled, determine coherence data indicative of the modification made by the one or more processors of the compute sled to the local working data in the memory, and send the coherence data to the second compute sled of the managed node.

公开(公告)号：US20180157424A1

公开(公告)日：2018-06-07

申请号：US15806240

申请日：2017-11-07

Applicant: INTEL CORPORATION

Inventor： Mark A. SCHMISSEUR ,  Mohan J. KUMAR ,  Balint FLEISCHER ,  Debendra DAS SHARMA ,  Raj Ramanujan

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0604 ,  G06F3/0607 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0665 ,  G06F3/0685 ,  G06F3/0688 ,  H04L41/0896 ,  H04L67/1097

Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.

公开(公告)号：US20180143678A1

公开(公告)日：2018-05-24

申请号：US15823527

申请日：2017-11-27

Applicant: Intel Corporation

Inventor： Mohan J. KUMAR ,  Murugasamy K. NACHIMUTHU

IPC: G06F1/32 ,  G06F9/4401

CPC classification number: G06F1/3206 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/4418 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

Abstract: A non-volatile random access memory (NVRAM) is used in a computer system to enhance support to sleep states. The computer system includes a processor, a non-volatile random access memory (NVRAM) that is byte-rewritable and byte-erasable, and power management (PM) module. A dynamic random access memory (DRAM) provides a portion of system address space. The PM module intercepts a request initiated by an operating system for entry into a sleep state, copies data from the DRAM to the NVRAM, maps the portion of the system address space from the DRAM to the NVRAM, and turns off the DRAM when transitioning into the sleep state. Upon occurrence of a wake event, the PM module returns control to the operating system such that the computer system resumes working state operations without the operating system knowing that the portion of the system address space has been mapped to the NVRAM.

公开(公告)号：US20160378353A1

公开(公告)日：2016-12-29

申请号：US14752812

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Mark A. SCHMISSEUR ,  Mohan J. KUMAR ,  Balint FLEISCHER ,  Debendra DAS SHARMA ,  Raj K. Ramanujan

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0685

Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.

Abstract translation: 提供了一种方法，系统，计算机可读存储介质和用于配置交换机以将存储设备中的分区分配给计算节点的交换机。 管理控制器配置交换机，以基于计算节点处的工作负载将至少一个存储设备的分区动态分配给计算节点。

公开(公告)号：US20240160431A1

公开(公告)日：2024-05-16

申请号：US18391637

申请日：2023-12-20

Applicant: Intel Corporation

Inventor： Mohan J. KUMAR ,  Murugasamy K. NACHIMUTHU ,  Daniel K. OSAWA ,  Maciej PLUCINSKI ,  Avinash CHANDRASEKARAN

IPC: G06F8/65 ,  G06F9/4401

CPC classification number: G06F8/65 ,  G06F9/4401

Abstract: Examples described herein relate to updating boot firmware code or microcode. In some examples, a management controller includes a memory and a system processor, coupled to the management controller, is to: based on a first configuration, perform a boot operation by a read of first boot firmware code from the memory of the management controller. Based on a second configuration, the system processor is to perform a boot operation by a read of second boot firmware code from a flash memory.