公开(公告)号：US20190355826A1

公开(公告)日：2019-11-21

申请号：US16474874

申请日：2017-04-11

Applicant: INTEL CORPORATION

Inventor： UYGAR E. AVCI ,  DANIEL H. MORRIS ,  IAN A. YOUNG

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/423

Abstract: Techniques are disclosed for forming semiconductor integrated circuits including a channel region, a gate dielectric between the gate electrode and the channel region, a first layer between the gate dielectric and the gate electrode, the first layer comprising temperature compensation material. In addition, the integrate circuit includes a source region adjacent to the channel region, a source metal contact on the source region, a drain region adjacent to the channel region, and a drain metal contact on the drain region. The temperature compensation material has a temperature dependent band structure, work-function, or polarization that dynamically adjusts the threshold voltage of the transistor in response to increased operating temperature to maintain the off-state current Ioff stable or otherwise within an acceptable tolerance. The temperature compensation material may be used in conjunction with a work function material to help provide desired performance at lower or non-elevated temperatures.

公开(公告)号：US20170287555A1

公开(公告)日：2017-10-05

申请号：US15088080

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： HUICHU LIU ,  SASIKANTH MANIPATRUNI ,  IAN A. YOUNG ,  TANAY KARNIK ,  DANIEL H. MORRIS ,  KAUSHIK VAIDYANATHAN

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2436 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/56 ,  G11C2213/79 ,  G11C2213/82 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: An apparatus is described that includes a resistive random access memory cell having a word line that is to receive a narrowed word line signal that limits an amount of time that an access transistor is on so as to limit the cell's high resistive state and/or the cell's low resistive state. Another apparatus is described that includes a resistive random access memory cell having SL and BL lines that are to receive respective signals having different voltage amplitudes to reduce source degeneration effects of the resistive random access memory cell's access transistor. Another apparatus is described that includes a resistive random access memory cell having a storage cell comprising a bottom-side OEL layer. Another apparatus is described that includes a resistive random access memory cell having a storage cell within a metal layer that resides between a pair of other metal layers where parallel SL and BL lines of the resistive random access memory cell respectively reside.