公开(公告)号：US20160278664A1

公开(公告)日：2016-09-29

申请号：US14671069

申请日：2015-03-27

Applicant: INTEL CORPORATION

Inventor： MONDIRA D. PANT ,  MEGGIE HAKIM ,  YOUSSRY BOTROS ,  TANAY KARNIK

IPC: A61B5/08 ,  A61B5/00

Abstract: A mechanism is described for facilitate dynamic and seamless breath testing at computing devices according to one embodiment. A method of embodiments, as described herein, includes detecting air exhaled by a user into a first computing device, where the air includes breath associated with the user. The method may further include sensing the breath in the air, obtaining a sample of the breath, and evaluating the sample, and generating a message based on the evaluation of the sample. The method may further include presenting, via one or more output components, the message to the user via a user interface, where the message includes results of the evaluation of the breath sample.

Abstract translation: 描述了根据一个实施例的用于促进计算设备处的动态和无缝呼吸测试的机制。 如本文所述的实施例的方法包括检测用户呼出到第一计算设备中的空气，其中空气包括与用户相关联的呼吸。 该方法还可以包括感测空气中的呼吸，获得呼吸样本，以及评估样本，以及基于样本的评估产生消息。 该方法还可以包括经由一个或多个输出组件经由用户界面向用户呈现消息，其中该消息包括呼吸样本的评估结果。

公开(公告)号：US20170287555A1

公开(公告)日：2017-10-05

申请号：US15088080

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： HUICHU LIU ,  SASIKANTH MANIPATRUNI ,  IAN A. YOUNG ,  TANAY KARNIK ,  DANIEL H. MORRIS ,  KAUSHIK VAIDYANATHAN

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2436 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/56 ,  G11C2213/79 ,  G11C2213/82 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

Abstract: An apparatus is described that includes a resistive random access memory cell having a word line that is to receive a narrowed word line signal that limits an amount of time that an access transistor is on so as to limit the cell's high resistive state and/or the cell's low resistive state. Another apparatus is described that includes a resistive random access memory cell having SL and BL lines that are to receive respective signals having different voltage amplitudes to reduce source degeneration effects of the resistive random access memory cell's access transistor. Another apparatus is described that includes a resistive random access memory cell having a storage cell comprising a bottom-side OEL layer. Another apparatus is described that includes a resistive random access memory cell having a storage cell within a metal layer that resides between a pair of other metal layers where parallel SL and BL lines of the resistive random access memory cell respectively reside.