公开(公告)号：US20180316524A1

公开(公告)日：2018-11-01

申请号：US15583644

申请日：2017-05-01

Applicant: INTEL CORPORATION

Inventor： Mor M. COHEN ,  Yaniv HADAR ,  Ehud U. SHOOR

IPC: H04L25/03 ,  H04L7/033

CPC classification number: H04L25/03949 ,  H04L7/00 ,  H04L7/033 ,  H04L25/03057 ,  H04L2201/02 ,  H04L2201/04

Abstract: An apparatus is provided which comprises: a data slicer to receive first data sampled by a data clock; an edge slicer to receive second data sampled by an edge clock; and a Least Mean Square (LMS) circuitry coupled to the data and edge slicers, wherein the LSM circuitry is to generate a code to adjust a phase of one of data clock and/or edge clock relative to one another.