公开(公告)号：US20220201836A1

公开(公告)日：2022-06-23

申请号：US17133234

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Arvind S ,  Raghavendra Rao ,  Geejagaaru Krishnamurthy Sandesh

IPC: H05K1/02 ,  H05K3/46

Abstract: A printed circuit board (PCB), comprising a first layer, the first layer comprising a first dielectric material substantially exclusively. The PCB also comprises a second layer, the second layer comprising the first dielectric material within a first region and a second dielectric material within a second region adjacent to first region. The first dielectric material has a first dielectric constant, a first coefficient of thermal expansion (CTE) and a first glass transition temperature (Tg). The second dielectric material has a second dielectric constant, a second CTE and a second Tg. The first dielectric constant is greater than the second dielectric constant. The first CTE is substantially equal to the second CTE; and the first Tg and the second Tg are greater than 150° C.

公开(公告)号：US11600544B2

公开(公告)日：2023-03-07

申请号：US16286736

申请日：2019-02-27

Applicant: INTEL CORPORATION

Inventor： Yogasundaram Chandiran ,  Geejagaaru Krishnamurthy Sandesh ,  Pradeep Ramesh ,  Ranjul Balakrishnan

IPC: H01L23/498 ,  H01L23/31 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18

Abstract: A PCB having a first surface and a second surface includes a trench extending through the PCB, a plurality of conductive traces on one or more sidewalls of the trench. The plurality of conductive traces extends through the PCB and may be arranged in pairs across from one another along at least a portion of the length of the trench. A first set of conductive contacts are arranged in a first zig-zag pattern around a perimeter of the trench. A second set of conductive contacts are arranged in a second zig-zag pattern around the perimeter of the trench. In some cases, the first and second zig-zag patterns are arranged with respect to one another around the perimeter of the trench in an alternating fashion. A chip package is also disclosed having a pin arrangement that couples to the corresponding arrangement of conductive contacts on the PCB.

公开(公告)号：US20230384842A1

公开(公告)日：2023-11-30

申请号：US17825558

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Siva Prasad Jangili Ganga ,  Shailendra Singh Chauhan ,  Abhijith Prabha ,  Geejagaaru Krishnamurthy Sandesh ,  Santhosh Ap

IPC: G06F1/18 ,  H05K7/14 ,  G06F1/16 ,  H05K7/20

CPC classification number: G06F1/185 ,  H05K7/1422 ,  G06F1/1633 ,  H05K7/2039

Abstract: An electronic system has a printed circuit board and a substrate. The substrate has two sides, a top and bottom. At least one memory unit is connected to the bottom side of the substrate and at least one processor is connected to the top side of the substrate. The memory is connected to the processor with interconnects that pass through the substrate.

公开(公告)号：US12120811B2

公开(公告)日：2024-10-15

申请号：US17133234

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Arvind S ,  Raghavendra Rao ,  Geejagaaru Krishnamurthy Sandesh

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/03

CPC classification number: H05K1/024 ,  H05K1/0231 ,  H05K1/0243 ,  H05K3/4673 ,  H05K3/4688 ,  H05K1/0306 ,  H05K1/036 ,  H05K1/0366 ,  H05K2201/0187

Abstract: A printed circuit board (PCB), comprising a first layer, the first layer comprising a first dielectric material substantially exclusively. The PCB also comprises a second layer, the second layer comprising the first dielectric material within a first region and a second dielectric material within a second region adjacent to first region. The first dielectric material has a first dielectric constant, a first coefficient of thermal expansion (CTE) and a first glass transition temperature (Tg). The second dielectric material has a second dielectric constant, a second CTE and a second Tg. The first dielectric constant is greater than the second dielectric constant. The first CTE is substantially equal to the second CTE; and the first Tg and the second Tg are greater than 150° C.

公开(公告)号：US20200273765A1

公开(公告)日：2020-08-27

申请号：US16286736

申请日：2019-02-27

Applicant: INTEL CORPORATION

Inventor： Yogasundaram Chandiran ,  Geejagaaru Krishnamurthy Sandesh ,  Pradeep Ramesh ,  Ranjul Balakrishnan

IPC: H01L23/31 ,  H01L23/498 ,  H05K1/18 ,  H05K1/02 ,  H05K1/11

Abstract: A PCB having a first surface and a second surface includes a trench extending through the PCB, a plurality of conductive traces on one or more sidewalls of the trench. The plurality of conductive traces extends through the PCB and may be arranged in pairs across from one another along at least a portion of the length of the trench. A first set of conductive contacts are arranged in a first zig-zag pattern around a perimeter of the trench. A second set of conductive contacts are arranged in a second zig-zag pattern around the perimeter of the trench. In some cases, the first and second zig-zag patterns are arranged with respect to one another around the perimeter of the trench in an alternating fashion. A chip package is also disclosed having a pin arrangement that couples to the corresponding arrangement of conductive contacts on the PCB.