公开(公告)号：US20240138077A1

公开(公告)日：2024-04-25

申请号：US18271544

申请日：2021-04-25

申请人： LG INNOTEK CO., LTD.

发明人： Jong Bae SHIN ,  Soo Min LEE ,  Jae Hun JEONG

IPC分类号： H05K3/46 ,  H05K1/11 ,  H05K3/00

CPC分类号： H05K3/4688 ,  H05K1/111 ,  H05K3/0014 ,  H05K3/4697 ,  H05K2201/0358

摘要： A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and including a cavity; a pad disposed on the first insulating layer and having a top surface exposed through the cavity; wherein the cavity of the second insulating layer includes: a bottom surface positioned higher than the top surface of the first insulating layer; and an inner wall extending from the bottom surface, wherein the inner wall includes: a first inner wall extending from the bottom surface and having a first inclination angle; and a second inner wall extending from the first inner wall and having a second inclination angle different from the first inclination angle.

公开(公告)号：US11917769B2

公开(公告)日：2024-02-27

申请号：US17768665

申请日：2021-03-04

申请人： SHENZHEN KINWONG ELECTRONIC CO., LTD.

发明人： Jun Wang ,  Xiaoqing Chen ,  Qian Chen

IPC分类号： H05K3/46 ,  H05K1/02 ,  H05K3/00

CPC分类号： H05K3/4611 ,  H05K1/0271 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/4688 ,  H05K2201/068 ,  H05K2201/09036 ,  H05K2203/061

摘要： The present application relates to the technical field of circuit board fabricating, and provides a method for fabricating an asymmetric board, the method includes fabricating a master board, fabricating a second sub-board, thermal compression bonding the master board and the second sub-board, and milling an asymmetric board; further includes at least one of the following three steps: laying copper on the connection areas of the master board except for the second copper layer of an outermost layer to obtain laying copper area, removing copper on the connection areas of the third copper layer, and after the step of milling the asymmetric board, on each of the sub-boards, performing depth control milling at the connection areas from a side of the second sub-board on each sub-board to obtain a depth control groove.

公开(公告)号：US20230290716A1

公开(公告)日：2023-09-14

申请号：US18013624

申请日：2021-06-29

申请人： LG INNOTEK CO., LTD

发明人： Jae Hun JEONG ,  Jong Bae SHIN ,  Soo Min LEE

IPC分类号： H01L23/498 ,  H05K1/02 ,  H05K3/46 ,  H01L21/48 ,  H05K3/00 ,  H05K1/03 ,  H01L23/13

CPC分类号： H01L23/49838 ,  H05K1/0298 ,  H05K3/4688 ,  H01L21/4857 ,  H05K3/0032 ,  H05K1/036 ,  H01L23/49894 ,  H01L23/49822 ,  H05K3/4697 ,  H01L23/13 ,  H05K1/186

摘要： A printed circuit board according to an embodiment comprises: a first insulation layer; a first circuit pattern disposed on one surface of the first insulation layer and including a pad; and a second insulation layer disposed on one surface of the first insulation layer and including a cavity exposing the pad, wherein the first circuit pattern includes a 1-1 metal layer disposed on one surface of the first insulation layer, and a 1-2 metal layer disposed on one surface of the 1-1 metal layer, wherein the area of the 1-1 metal layer is greater than the area of the 1-2 metal layer, and at least a portion of a side surface of the 1-1 metal layer is exposed through the cavity.

公开(公告)号：US20190215959A1

公开(公告)日：2019-07-11

申请号：US16245396

申请日：2019-01-11

申请人： IBIDEN CO., LTD.

发明人： Takema ADACHI ,  Toshihide MAKINO ,  Hidetoshi NOGUCHI

IPC分类号： H05K1/11 ,  H05K3/46 ,  H05K3/40

CPC分类号： H05K1/116 ,  H05K1/113 ,  H05K3/4015 ,  H05K3/4655 ,  H05K3/4688

摘要： A printed wiring board includes a core substrate, a first build-up layer, and a second build-up layer. The core substrate includes a core layer, through-hole conductors and through-hole lands. Metal foils of the through-hole lands in the core substrate have mat surfaces at interfaces of the core layer in the core substrate, metal foils of via lands in the build-up layers have inner mat surfaces at interfaces of insulating layers, and metal foils of outermost conductor layers in the build-up layers have outermost mat surfaces at interfaces of outermost insulating layers. Ten-point average roughness (RzI1) of the inner first mat surface is smaller than each of ten-point average roughness (Rz1, Rz2) of the mat surfaces and ten-point average roughness (RzO1, RzO2) of the outermost mat surfaces. Ten-point average roughness (RzI2) of the inner second mat surface is smaller than each of the ten-point average roughness (Rz1, Rz2, RzO1, RzO2).

公开(公告)号：US20180332707A1

公开(公告)日：2018-11-15

申请号：US16043603

申请日：2018-07-24

申请人： FUJITSU LIMITED

发明人： Tomoyuki Akahoshi ,  Daisuke Mizutani

IPC分类号： H05K1/16 ,  H05K1/11 ,  H05K3/42 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02 ,  H05K3/00 ,  H01G4/12 ,  H01G4/33

CPC分类号： H05K1/162 ,  H01G4/012 ,  H01G4/12 ,  H01G4/1227 ,  H01G4/232 ,  H01G4/33 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L28/60 ,  H05K1/024 ,  H05K1/115 ,  H05K1/16 ,  H05K3/0026 ,  H05K3/422 ,  H05K3/423 ,  H05K3/46 ,  H05K3/4688 ,  H05K2201/093 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/107

摘要： A substrate includes: a signal line via, a ground line via, and a power supply line via; a first group of first conductor layers formed at a first wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a second conductor layer formed at a second wiring layer level and coupled to the power supply line via; a second group of third conductor layers formed at a third wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a first insulating layer; and a second insulating layer, wherein the second insulating layer has an opening with a third insulating layer, a relative dielectric constant of the second insulating layer is higher than the first insulating layer and the third insulating layer, and the opening reaches a conductor pattern.

公开(公告)号：US10015885B2

公开(公告)日：2018-07-03

申请号：US14655627

申请日：2013-12-20

申请人： LG INNOTEK CO., LTD.

发明人： Won Suk Jung ,  Yun Ho An ,  Sang Myung Lee ,  Joon Wook Han

IPC分类号： H05K1/18 ,  H05K1/11 ,  H05K3/46 ,  H05K3/30 ,  H05K3/18

CPC分类号： H05K1/185 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2924/15153 ,  H05K1/115 ,  H05K1/183 ,  H05K3/181 ,  H05K3/30 ,  H05K3/4611 ,  H05K3/4688 ,  H05K2201/09563 ,  H05K2201/10121 ,  H05K2201/10151 ,  Y10T156/10

摘要： Provided are a printed circuit board and a method of manufacturing the printed circuit board, the printed circuit board including: a first element and a second element; a first base substrate including an embedding part in which the first element is embedded and a cavity into which the second element is mounted; and a second base substrate bonded to one surface of the first base substrate and including a first via for the second element.

公开(公告)号：US10008452B2

公开(公告)日：2018-06-26

申请号：US15469964

申请日：2017-03-27

申请人： INTEL CORPORATION

发明人： Qing Ma ,  Johanna M. Swan ,  Robert Starkston ,  John S. Guzek ,  Robert L. Sankman ,  Aleksandar Aleksov

IPC分类号： H01L29/40 ,  H01L23/538 ,  H01L23/15 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L21/683

CPC分类号： H01L23/5386 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08238 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2924/20641 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/185 ,  H05K3/4688 ,  H05K2201/017 ,  H05K2203/1469 ,  Y10T156/1057 ,  H01L2924/014 ,  H01L2924/00

摘要： Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.

公开(公告)号：US20180122733A1

公开(公告)日：2018-05-03

申请号：US15853926

申请日：2017-12-25

申请人： Unimicron Technology Corp.

发明人： Yu-Hua CHEN ,  Cheng-Ta KO

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/096 ,  H05K2201/10378

摘要： A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.

公开(公告)号：US09942980B2

公开(公告)日：2018-04-10

申请号：US15123215

申请日：2014-05-28

申请人： INTEL CORPORATION

发明人： Chuan Hu ,  Adel A. Elsherbini ,  Yoshihiro Tomita ,  Shawna Liff

IPC分类号： H01L23/538 ,  H05K1/02 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H05K1/18

CPC分类号： H05K1/0283 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49894 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/1515 ,  H01L2924/181 ,  H05K1/036 ,  H05K1/185 ,  H05K3/1275 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/09018 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09263 ,  H05K2201/10151 ,  H01L2924/00012

摘要： Embodiments of the present disclosure describe a wavy interconnect for bendable and stretchable devices and associated techniques and configurations. In one embodiment, an interconnect assembly includes a flexible substrate defining a plane and a wavy interconnect disposed on the flexible substrate and configured to route electrical signals of an integrated circuit (IC) device in a first direction that is coplanar with the plane, the wavy interconnect having a wavy profile from a second direction that is perpendicular to the first direction and coplanar with the plane. Other embodiments may be described and/or claimed.

公开(公告)号：US20180077803A1

公开(公告)日：2018-03-15

申请号：US15261838

申请日：2016-09-09

申请人： QUALCOMM Incorporated

发明人： Changhan Hobie YUN ,  David Francis BERDY ,  Chengjie ZUO ,  Jonghae KIM ,  Niranjan Sunil MUDAKATTE ,  Mario Francisco VELEZ ,  Shiqun GU

IPC分类号： H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H05K3/30 ,  H05K3/40

CPC分类号： H05K1/185 ,  H01G4/224 ,  H01G4/236 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/52 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4682 ,  H05K3/4688

摘要： Due to the presence of a glass substrate, it is difficult to fabricate thin conventional passive-on-glass (POG) devices. Also glass dicing has been a throughput bottleneck in fabricating the conventional POG device. To address such disadvantages, devices without the glass substrates are proposed. Support structures may be provided to provide mechanical support. The devices are significantly thinner and allow access to the passive components from both first and second surfaces, which are opposite and exposed surfaces. The proposed POM devices may also be incorporated in a package substrate.