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公开(公告)号：US20210382720A1
公开(公告)日：2021-12-09
申请号：US17131647
申请日：2020-12-22
Applicant: Intel Corporation
Inventor： Sabareesh GANAPATHY , Fangwen FU , Hong JIANG , James VALERIO
Abstract: Examples described herein relate to a graphics processing unit (GPU) coupled to the memory device, the GPU configured to: execute an instruction thread; determine if a dual directional signal barrier is associated with the instruction thread; and based on clearance of the dual directional signal barrier for a particular signal barrier identifier and a mode of operation, indicate a clearance of the dual directional signal barrier for the mode of operation, wherein the dual directional signal barrier is to provide a single barrier to gate activity of one or more producers based on activity of one or more consumers or gate activity of one or more consumers based on activity of one or more producers.
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公开(公告)号：US20160048949A1
公开(公告)日：2016-02-18
申请号：US14774639
申请日：2014-03-26
Applicant: INTEL CORPORATION
Inventor： Ya-Ti PENG , Yi-Jen CHIU , Hong JIANG
CPC classification number: G06T5/001 , G06T5/20 , G06T7/90 , G06T2207/10024 , H04N1/628
Abstract: Techniques related to skin tone tuned image enhancement are described. Such techniques may include performing an enhancement of a pixel of an input image based on a skin tone detection score and local detail information of the pixel.
Abstract translation: 描述了与肤色调整图像增强相关的技术。 这样的技术可以包括基于肤色检测得分和像素的局部细节信息来执行输入图像的像素的增强。
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公开(公告)号：US20210382717A1
公开(公告)日：2021-12-09
申请号：US16892202
申请日：2020-06-03
Applicant: Intel Corporation
Inventor： Hong JIANG , Sabareesh GANAPATHY , Xinmin TIAN , Fangwen FU , James VALERIO
Abstract: Examples described herein relate to a graphics processing apparatus that includes a memory device and a graphics processing unit (GPU) coupled to the memory device, the GPU can be configured to: execute an instruction thread; determine if a signal barrier is associated with the instruction thread; for a signal barrier associated with the instruction thread, determine if the signal barrier is cleared; and based on the signal barrier being cleared, permit any waiting instruction thread associated with the signal barrier identifier to commence with execution but not permit any waiting thread that is not associated with the signal barrier identifier to commence with execution. In some examples, the signal barrier includes a signal barrier identifier. In some examples, the signal barrier identifier is one of a plurality of values. In some examples, a gateway is used to receive indications of a signal barrier identifier and to selectively clear a signal barrier for a waiting instruction thread associated with the signal barrier identifier based on clearance conditions associated with the signal barrier being met.
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4.发明申请公开(公告)号：US20180316937A1
公开(公告)日：2018-11-01
申请号：US15961677
申请日：2018-04-24
Applicant: Intel Corporation
Inventor： Wenhao ZHANG , Yi-Jen CHIU , Lidong XU , Yu HAN , Hong JIANG
CPC classification number: H04N19/63 , H04N19/132 , H04N19/157 , H04N19/18 , H04N19/30 , H04N19/36
Abstract: Methods, systems, and computer program products for the generation of multiple layers of scaled encoded video data compatible with the HEVC standard. Residue from prediction processing may be transformed into coefficients in the frequency domain. The coefficients may then be sampled to create a layer of encoded data. The coefficients may be sampled in different ways to create multiple respective layers. The layers may then be multiplexed and sent to a decoder. There, one or more of the layers may be chosen. The choice of certain layer(s) may be dependent on the desired attributes of the resulting video. A certain level of video quality, frame rate, resolution, and/or bit depth may be desired, for example. The coefficients in the chosen layers may then be assembled to create a version of the residue to be used in video decoding.
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