公开(公告)号：US20190042514A1

公开(公告)日：2019-02-07

申请号：US16049607

申请日：2018-07-30

Applicant: Intel Corporation

Inventor： Anand K. ENAMANDRAM ,  Sivakumar RADHAKRISHNAN ,  Jayasekhar THOLIYIL ,  Tina C. ZHONG ,  Malay TRIVEDI

IPC: G06F13/40 ,  G06F9/4401 ,  G06F9/445 ,  G06F13/16 ,  G06F13/42

Abstract: Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.

公开(公告)号：US20190034264A1

公开(公告)日：2019-01-31

申请号：US15846170

申请日：2017-12-18

Applicant: INTEL CORPORATION

Inventor： Sivakumar RADHAKRISHNAN ,  Malay TRIVEDI ,  Jayasekhar THOLIYIL ,  Erik A. MCSHANE ,  Roger W. LIU ,  Mahesh S. NATU

IPC: G06F11/07

Abstract: An error handling device logs errors in a computing system including a plurality of devices connected to the error handling device. The error handling device provides groups of error registers. Each group of error registers is associated with a value of a plurality of values. Each of the devices that communicate errors to the error handling device are associated with one of the values. The error handling device receives error messages from the devices connected to the error handling device and for each received error message of the received error messages, determines a value of the plurality of values associated with the device transmitting the received error message, determines the group of error registers associated with the determined value, and log the received error message in the determined group of error registers.