公开(公告)号：US11947995B2

公开(公告)日：2024-04-02

申请号：US16878064

申请日：2020-05-19

Applicant: Intel Corporation

Inventor： Kuan Hua Tan ,  Sahar Khalili ,  Eng Hun Ooi ,  Shrinivas Venkatraman ,  Dimpesh Patel

IPC: G06F9/54 ,  G06F9/46 ,  G06F11/30 ,  G06F13/16 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F9/467 ,  G06F9/546 ,  G06F11/3037 ,  G06F13/1668 ,  G06F13/385 ,  G06F13/4221 ,  G06F2213/0026 ,  G06F2213/3808

Abstract: A multilevel memory system includes a nonvolatile memory (NVM) device with an NVM media having a media write unit that is different in size than a host write unit of a host controller of the system that has the multilevel memory system. The memory device includes a media controller that controls writes to the NVM media. The host controller sends a write transaction to the media controller. The write transaction can include the write data in host write units, while the media controller will commit data in media write units to the NVM media. The media controller can send a transaction message to indicate whether the write data for the write transaction was successfully committed to the NVM media.

公开(公告)号：US11704275B2

公开(公告)日：2023-07-18

申请号：US17387261

申请日：2021-07-28

Applicant: Intel Corporation

Inventor： Kuan Hua Tan ,  Eng Hun Ooi ,  Ang Li

IPC: G06F13/42 ,  G06F9/445

CPC classification number: G06F13/4221 ,  G06F9/44505 ,  G06F2213/0026

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

公开(公告)号：US20190220422A1

公开(公告)日：2019-07-18

申请号：US16367846

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Kuan Hua Tan ,  Ang Li ,  Eng Hun Ooi

IPC: G06F13/16 ,  G06F1/3234 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/50

CPC classification number: G06F13/161 ,  G06F1/3206 ,  G06F1/3253 ,  G06F9/30101 ,  G06F9/5005 ,  G06F2213/0026

Abstract: Systems and devices can include a power management controller to determine a low power mode exit timing from a plurality of low power mode exit timing options, and cause the setting of a low power mode control register based on the determined low power mode exit timing. A message generator can generate a power mode request message. The power mode request message indicating the determined low power mode exiting timing. The power mode request message can be transmitted to a host across a multilane link.

公开(公告)号：US20190042155A1

公开(公告)日：2019-02-07

申请号：US15978766

申请日：2018-05-14

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Shrinivas Venkatraman ,  Kuan Hua Tan ,  Ang Li ,  Sahar Khalili ,  Su Wei Lim ,  Robert Royer, JR.

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/06

Abstract: Systems, apparatuses and methods may provide for technology to add non-address metadata to a memory address field of a transaction layer packet (TLP), wherein the non-address metadata includes one or more vendor-specific attributes. Additionally, the technology may coordinate between a transmitter and a receiver to prevent the TLP from violating an address boundary constraint associated with an interface. In one example, the address boundary constraint prohibits an address and length combination of the TLP from crossing a 4-KB boundary.

公开(公告)号：US20190340148A1

公开(公告)日：2019-11-07

申请号：US16513941

申请日：2019-07-17

Applicant: Intel Corporation

Inventor： Kuan Hua Tan ,  Eng Hun Ooi ,  Ang Li

IPC: G06F13/42 ,  G06F9/445

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

公开(公告)号：US20210357350A1

公开(公告)日：2021-11-18

申请号：US17387261

申请日：2021-07-28

Applicant: Intel Corporation

Inventor： Kuan Hua Tan ,  Eng Hun Ooi ,  Ang Li

IPC: G06F13/42 ,  G06F9/445

Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

公开(公告)号：US10942672B2

公开(公告)日：2021-03-09

申请号：US16422827

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Shrinivas Venkatraman ,  Eng Hun Ooi ,  Sahar Khalili ,  Dimpesh Patel ,  Kuan Hua Tan

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/42

Abstract: Apparatuses, storage media and methods associated with data transfer, are disclosed herein. In some embodiments, an apparatus for computing comprises: a commit generator and a media write generator. The commit generator is arranged to generate commit indicators correspondingly associated with media slices of a storage media to respectively denote to a storage media controller of the storage media whether to proceed with writing the media slices into the storage media. The media write generator is arranged provide data chunks of the media slices to be written into the storage media, and the associated commit indicators to the storage media controller. A size of each data chunk is smaller than a size of each media slice. Other embodiments are also described and claimed.

公开(公告)号：US20190114281A1

公开(公告)日：2019-04-18

申请号：US16219922

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Ang Li ,  Kuan Hua Tan

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and device can involve an application layer logic implemented at least partially in hardware circuitry; a first port for transmitting information across a multi-lane link, the first port comprising a protocol stack; a memory element, the memory element comprising mapping between an event identifier value and an event identifier carrier value, the event identifier identifying an event to be carried out by the application layer logic across the multi-lane link, the event identifier carrier value mapped to the event identifier, the application layer logic to transmit the event identifier carrier value across the link prior to executing the event.

公开(公告)号：US20190095554A1

公开(公告)日：2019-03-28

申请号：US15718110

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Eng Hun Ooi ,  Su Wei Lim ,  Kuan Hua Tan ,  Prashanth Kalluraya

IPC: G06F17/50 ,  G06F13/42

Abstract: Aspects of the embodiments are directed to systems and methods for emulating a PCIe root complex integrated endpoint. The systems and methods can include hardware logic implemented in a root complex system-on-chip and/or a connected device. The hardware can receive a request message to access one or more registers of a hardware device; determine that the request message includes a request to access one or more Peripheral Component Interconnect Express (PCIe)-specific registers; and respond to the request message without providing information associated with the one or more PCIe-specific registers.

公开(公告)号：US11907035B2

公开(公告)日：2024-02-20

申请号：US16875898

申请日：2020-05-15

Applicant: Intel Corporation

Inventor： Ang Li ,  David J. Harriman ,  Kuan Hua Tan

IPC: G06F1/28 ,  G06F13/42 ,  G06F1/04

CPC classification number: G06F1/28 ,  G06F1/04 ,  G06F13/4221 ,  G06F13/4295 ,  G06F2213/0026

Abstract: An interface of a device is used to couple to another device and includes a set of data pins to support high speed data communication on an interconnect link between the devices based on an interconnect protocol. The interface further includes at least one auxiliary pin to support a particular signal defined by the interconnect protocol. The device is further configurated to generate hint data for use by the other device and send the hint data as a sideband signal to the other device over the auxiliary pin, where the sideband signal is distinct from signals defined for the auxiliary pin by the interconnect protocol.