公开(公告)号：US09223714B2

公开(公告)日：2015-12-29

申请号：US13836374

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Mauricio Breternitz ,  Youfeng Wu ,  Peter Sassone ,  James Mason ,  Aashish Phansalkar ,  Balaji Vijayan

IPC: G06F9/30 ,  G06F12/08 ,  G06F9/38

CPC classification number: G06F12/0875 ,  G06F9/30 ,  G06F9/30152 ,  G06F9/3802 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3842 ,  G06F12/0886

Abstract: A system, processor, and method to predict with high accuracy and retain instruction boundaries for previously executed instructions in order to decode variable length instructions is disclosed. In at least one embodiment, a disclosed processor includes an instruction fetch unit, an instruction cache, a boundary byte predictor, and an instruction decoder. In some embodiments, the instruction fetch unit provides an instruction address and the instruction cache produces an instruction tag and instruction cache content corresponding to the instruction address. The instruction decoder, in some embodiments, includes boundary byte logic to determine an instruction boundary in the instruction cache content.

Abstract translation: 公开了一种以高精度预测并保留先前执行的指令的指令边界以便解码可变长度指令的系统，处理器和方法。 在至少一个实施例中，所公开的处理器包括指令提取单元，指令高速缓存，边界字节预测器和指令解码器。 在一些实施例中，指令获取单元提供指令地址，并且指令高速缓冲存储器产生与指令地址对应的指令标签和指令高速缓存内容。 在一些实施例中，指令解码器包括用于确定指令高速缓存内容中的指令边界的边界字节逻辑。

公开(公告)号：US09146844B2

公开(公告)日：2015-09-29

申请号：US13893238

申请日：2013-05-13

Applicant: INTEL CORPORATION

Inventor： Mauricio Breternitz ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

IPC: G06F11/36 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Abstract translation: 本文描述了用于有条件地提交和/或推测性检查点事务的装置和方法，这可能导致事务的动态调整大小。 在二进制代码的动态优化期间，插入事务以提供存储器排序保护措施，这使得动态优化器能够更积极地优化代码。 并且条件提交可以有效地执行动态优化代码，同时尝试防止事务用尽硬件资源。 虽然投机检查点能够在中止交易后快速有效地恢复。 处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。 并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。