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    DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS
    2.
    发明申请
    DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS 审中-公开

    公开(公告)号：US20190332158A1

    公开(公告)日：2019-10-31

    申请号：US16508916

    申请日：2019-07-11

    Applicant: Intel Corporation

    Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

    IPC: G06F1/329 ,  G06F9/50 ,  G06F9/48 ,  G06F11/34 ,  G06F9/445 ,  G06F1/3287 ,  G06F9/38

    Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

    Dynamic core selection for heterogeneous multi-core systems
    5.
    发明授权
    Dynamic core selection for heterogeneous multi-core systems 有权
    异构多核系统的动态核心选择

    公开(公告)号：US09501135B2

    公开(公告)日：2016-11-22

    申请号：US14169955

    申请日：2014-01-31

    Applicant: INTEL CORPORATION

    Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

    IPC: G06F1/32 ,  G06F9/38 ,  G06F9/50 ,  G06F9/445 ,  G06F9/48 ,  G06F11/34

    CPC classification number: G06F1/329 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/445 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5094 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2209/501 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/34 ,  Y02D50/20

    Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

    Abstract translation: 可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。 可以用信号通知第二处理核心的加电。 可以收集执行程序代码的第一处理核心的第一性能度量。 当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。 当第一性能度量不比先前确定的核心性能度量好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

    Modified execution using context sensitive auxiliary code
    6.
    发明授权
    Modified execution using context sensitive auxiliary code 有权
    使用上下文相关的辅助代码修改执行

    公开(公告)号：US09342303B2

    公开(公告)日：2016-05-17

    申请号：US13843940

    申请日：2013-03-15

    Applicant: Intel Corporation

    Inventor： James E. Smith ,  Denis M. Khartikov ,  Shiliang Hu ,  Youfeng Wu

    IPC: G06F9/30 ,  G06F9/45

    CPC classification number: G06F9/30 ,  G06F8/443 ,  G06F9/30181 ,  G06F9/328

    Abstract: A system and method to enhance execution of architected instructions in a processor uses auxiliary code to optimize execution of base microcode. An execution context of the architected instructions may be profiled to detect potential optimizations, resulting in generation and storage of auxiliary microcode. When the architected instructions are decoded to base microcode for execution, the base microcode may be enhanced or modified using retrieved auxiliary code.

    Abstract translation: 用于增强处理器中的架构指令执行的系统和方法使用辅助代码来优化基本微代码的执行。 可以对构建的指令的执行上下文进行分析以检测潜在的优化，从而产生和存储辅助微代码。 当结构化指令被解码为基本微代码以执行时，可以使用检索的辅助代码来增强或修改基本微代码。

    Processor with memory race recorder to record thread interleavings in multi-threaded software
    7.
    发明授权
    Processor with memory race recorder to record thread interleavings in multi-threaded software 有权
    具有内存种族记录器的处理器可在多线程软件中记录线程交错

    公开(公告)号：US09128781B2

    公开(公告)日：2015-09-08

    申请号：US13729718

    申请日：2012-12-28

    Applicant: Intel Corporation

    Inventor： Tim Kranich ,  Gilles A. Pokam ,  Justin E. Gottschlich ,  Klaus Danne ,  Rolf Kassa ,  Shiliang Hu ,  Cristiano L. Pereira

    IPC: G06F9/52 ,  G06F11/36

    CPC classification number: G06F9/526 ,  G06F11/3404 ,  G06F11/3409 ,  G06F11/3471 ,  G06F11/36 ,  G06F11/3636

    Abstract: A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes memory access monitor logic to monitor accesses to memory by the first thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads. The logic includes chunk generation logic is to generate chunks to represent committed execution of the first thread. Each of the chunks is to include a number of instructions of the first thread executed and committed and a time stamp. The chunk generation logic is to stop generation of a current chunk in response to detection of a data race by the memory access monitor logic. A chunk buffer is to temporarily store chunks until the chunks are transferred out of the processor.

    Abstract translation: 处理器包括执行第一软件线程的第一核，执行第二软件线程的第二核和共享存储器存取监视和记录逻辑。 该逻辑包括存储器访问监视器逻辑，以监视第一线程对存储器的访问，记录被监视的访问的存储器地址，以及检测与其他线程相关的记录存储器地址的数据比赛。 逻辑包括块生成逻辑是生成块来表示第一个线程的提交执行。 每个块都包括执行和提交的第一个线程的一些指令和一个时间戳。 块生成逻辑是通过存储器访问监视器逻辑来检测数据竞赛来停止生成当前块。 块缓冲区是临时存储块，直到块被从处理器传出。

    Dynamic core selection for heterogeneous multi-core systems
    8.
    发明授权
    Dynamic core selection for heterogeneous multi-core systems 有权

    公开(公告)号：US10534424B2

    公开(公告)日：2020-01-14

    申请号：US14986676

    申请日：2016-01-02

    Applicant: Intel Corporation

    Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

    IPC: G06F1/329 ,  G06F1/3287 ,  G06F9/38 ,  G06F9/50 ,  G06F11/34 ,  G06F9/445 ,  G06F9/48

    Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

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