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    DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS
    2.
    发明申请
    DYNAMIC CORE SELECTION FOR HETEROGENEOUS MULTI-CORE SYSTEMS 审中-公开

    公开(公告)号：US20190332158A1

    公开(公告)日：2019-10-31

    申请号：US16508916

    申请日：2019-07-11

    Applicant: Intel Corporation

    Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

    IPC: G06F1/329 ,  G06F9/50 ,  G06F9/48 ,  G06F11/34 ,  G06F9/445 ,  G06F1/3287 ,  G06F9/38

    Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

    Technologies for position-independent persistent memory pointers
    3.
    发明授权
    Technologies for position-independent persistent memory pointers 有权

    公开(公告)号：US09971703B2

    公开(公告)日：2018-05-15

    申请号：US15672425

    申请日：2017-08-09

    Applicant: Intel Corporation

    Inventor： Marcelo S. Cintra ,  Cheng Wang ,  Youfeng Wu ,  Alexandre Xavier DuChateau

    IPC: G06F12/1009 ,  G06F12/02

    CPC classification number: G06F12/1009 ,  G06F8/447 ,  G06F9/3836 ,  G06F9/44568 ,  G06F12/0238 ,  G06F12/0292 ,  G06F2212/1044

    Abstract: Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may load a persistent memory pointer having a static region identifier, a segment identifier, and an offset from the persistent memory. The computing device may map the static region identifier to a dynamic region identifier and determine a virtual memory address of the persistent memory pointer target based on the dynamic region identifier, the segment identifier, and the offset. The computing device may load an in-storage representation of a persistent-export pointer from the persistent memory, map the in-storage representation to a runtime representation, and determine a target address of a persistent external data object based on the runtime representation. The computing device may include a compiler to generate output code including persistent memory pointer and/or persistent-export pointer accesses. Other embodiments are described and claimed.

    Instruction boundary prediction for variable length instruction set
    4.
    发明授权
    Instruction boundary prediction for variable length instruction set 有权
    可变长度指令集的指令边界预测

    公开(公告)号：US09223714B2

    公开(公告)日：2015-12-29

    申请号：US13836374

    申请日：2013-03-15

    Applicant: Intel Corporation

    Inventor： Mauricio Breternitz ,  Youfeng Wu ,  Peter Sassone ,  James Mason ,  Aashish Phansalkar ,  Balaji Vijayan

    IPC: G06F9/30 ,  G06F12/08 ,  G06F9/38

    CPC classification number: G06F12/0875 ,  G06F9/30 ,  G06F9/30152 ,  G06F9/3802 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3842 ,  G06F12/0886

    Abstract: A system, processor, and method to predict with high accuracy and retain instruction boundaries for previously executed instructions in order to decode variable length instructions is disclosed. In at least one embodiment, a disclosed processor includes an instruction fetch unit, an instruction cache, a boundary byte predictor, and an instruction decoder. In some embodiments, the instruction fetch unit provides an instruction address and the instruction cache produces an instruction tag and instruction cache content corresponding to the instruction address. The instruction decoder, in some embodiments, includes boundary byte logic to determine an instruction boundary in the instruction cache content.

    Abstract translation: 公开了一种以高精度预测并保留先前执行的指令的指令边界以便解码可变长度指令的系统，处理器和方法。 在至少一个实施例中，所公开的处理器包括指令提取单元，指令高速缓存，边界字节预测器和指令解码器。 在一些实施例中，指令获取单元提供指令地址，并且指令高速缓冲存储器产生与指令地址对应的指令标签和指令高速缓存内容。 在一些实施例中，指令解码器包括用于确定指令高速缓存内容中的指令边界的边界字节逻辑。

    Dynamic optimization of pipelined software
    5.
    发明授权
    Dynamic optimization of pipelined software 有权
    流水线软件的动态优化

    公开(公告)号：US09170792B2

    公开(公告)日：2015-10-27

    申请号：US14126463

    申请日：2013-05-30

    Applicant: Intel Corporation

    Inventor： Hyunchul Park ,  Hongbo Rong ,  Youfeng Wu

    IPC: G06F9/45

    CPC classification number: G06F8/4452 ,  G06F8/441 ,  G06F8/443 ,  G06F8/4451 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3863

    Abstract: In an embodiment, a system includes a processor including at least one core to execute operations of a loop that includes S stages. The system also includes stage insertion means for adding a delay stage to the loop to increase a lifetime of a corresponding register associated with a first variable of the loop and to delay storage of contents of the register. The system also includes a dynamic random access memory (DRAM). Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，系统包括处理器，其包括至少一个核，以执行包括S级的循环的操作。 该系统还包括阶段插入装置，用于向环路增加延迟级，以增加与循环的第一变量相关联的相应寄存器的寿命并延迟存储寄存器的内容。 该系统还包括动态随机存取存储器（DRAM）。 描述和要求保护其他实施例。

    Dynamic core selection for heterogeneous multi-core systems
    7.
    发明授权
    Dynamic core selection for heterogeneous multi-core systems 有权

    公开(公告)号：US10437319B2

    公开(公告)日：2019-10-08

    申请号：US14986678

    申请日：2016-01-02

    Applicant: Intel Corporation

    Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

    IPC: G06F1/329 ,  G06F1/3287 ,  G06F9/38 ,  G06F9/50 ,  G06F11/34 ,  G06F9/445 ,  G06F9/48

    Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

    OPTIMIZED CALL RETURN
    10.
    发明申请
    OPTIMIZED CALL RETURN 审中-公开

    公开(公告)号：US20180285113A1

    公开(公告)日：2018-10-04

    申请号：US15475389

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Hou-Jen Ko ,  Girish Venkatasubramanian ,  Jason Agron ,  Tyler Sondag ,  Youfeng Wu

    IPC: G06F9/30

    CPC classification number: G06F9/30174 ,  G06F9/3016

    Abstract: In one example a processor includes a region formation engine to identify a region of code for translation from a guest instruction set architecture to a native instruction set architecture. The processor also includes a binary translator to translate the region of code. The region formation engine is to perform aggressive region formation, which includes forming a region across a boundary of a return instruction. The translated region of code is to prevent a side entry into the translated region of code at a translated return target instruction included in the translated region of code. In more specific examples, performing aggressive region formation includes a region formation grow phase and a region formation cleanup phase. In the grow phase priority may be given to growing complete paths from a call target to a corresponding return. The region formation cleanup phase may comprise eliminating call targets that are not reachable.

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