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    Odd index precomputation for authentication path computation
    1.
    发明授权
    Odd index precomputation for authentication path computation 有权

    公开(公告)号：US11770262B2

    公开(公告)日：2023-09-26

    申请号：US17568919

    申请日：2022-01-05

    Applicant: Intel Corporation

    Inventor： Rafael Misoczki ,  Vikram Suresh ,  Santosh Ghosh ,  Manoj Sastry ,  Sanu Mathew ,  Raghavan Kumar

    IPC: H04L9/08 ,  H04L9/00 ,  H04L9/32

    CPC classification number: H04L9/3247 ,  H04L9/085 ,  H04L9/0852 ,  H04L9/50

    Abstract: In one example an apparatus comprises a computer-readable memory, signature logic to compute a message hash of an input message using a secure hash algorithm, process the message hash to generate an array of secret key components for the input message, apply a hash chain function to the array of secret key components to generate an array of signature components, the hash chain function comprising a series of even-index hash chains and a series of odd-index hash chains, wherein the even-index hash chains and the odd-index hash chains generate a plurality of intermediate node values and a one-time public key component between the secret key components and the signature components and store at least some of the intermediate node values in the computer-readable memory for use in one or more subsequent signature operations. Other examples may be described.

    Post quantum public key signature operation for reconfigurable circuit devices
    3.
    发明授权
    Post quantum public key signature operation for reconfigurable circuit devices 有权

    公开(公告)号：US11205017B2

    公开(公告)日：2021-12-21

    申请号：US16456339

    申请日：2019-06-28

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sanu Mathew ,  Rafael Misoczki ,  Santosh Ghosh ,  Raghavan Kumar ,  Manoj Sastry ,  Andrew H. Reinders

    IPC: G06F21/72 ,  G06F21/76 ,  H04L9/32 ,  H04L9/08

    Abstract: Embodiments are directed to post quantum public key signature operation for reconfigurable circuit devices. An embodiment of an apparatus includes one or more processors; and a reconfigurable circuit device, the reconfigurable circuit device including a dedicated cryptographic hash hardware engine, and a reconfigurable fabric including logic elements (LEs), wherein the one or more processors are to configure the reconfigurable circuit device for public key signature operation, including mapping a state machine for public key generation and verification to the reconfigurable fabric, including mapping one or more cryptographic hash engines to the reconfigurable fabric, and combining the dedicated cryptographic hash hardware engine with the one or more mapped cryptographic hash engines for cryptographic signature generation and verification.

    DEVICE, SYSTEM, AND METHOD TO CHANGE A CONSISTENCY OF BEHAVIOR BY A CELL CIRCUIT
    6.
    发明申请
    DEVICE, SYSTEM, AND METHOD TO CHANGE A CONSISTENCY OF BEHAVIOR BY A CELL CIRCUIT 审中-公开

    公开(公告)号：US20200312404A1

    公开(公告)日：2020-10-01

    申请号：US16417538

    申请日：2019-05-20

    Applicant: Intel Corporation

    Inventor： Vivek De ,  Sanu Mathew ,  Sudhir Satpathy ,  Vikram Suresh ,  Raghavan Kumar

    IPC: G11C11/419 ,  H04L9/32

    Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.

    APPARATUS AND METHOD FOR GENERATING HYBRID STATIC/DYNAMIC ENTROPY PHYSICALLY UNCLONABLE FUNCTION
    8.
    发明申请
    APPARATUS AND METHOD FOR GENERATING HYBRID STATIC/DYNAMIC ENTROPY PHYSICALLY UNCLONABLE FUNCTION 审中-公开

    公开(公告)号：US20190305970A1

    公开(公告)日：2019-10-03

    申请号：US15942181

    申请日：2018-03-30

    Applicant: Intel Corporation

    Inventor： Sudhir Satpathy ,  Vikram Suresh ,  Sanu Mathew

    IPC: H04L9/32 ,  H04L9/00

    Abstract: An apparatus is provided which comprises: an entropy source to produce a first random sequence of bits, wherein the entropy source comprises an array of bi-stable cross-coupled inverter cells; a first circuitry coupled to the entropy source, wherein the first circuitry to generate an entropy source selection set; and a second circuitry coupled to the entropy source and the first circuitry, wherein the second circuitry is to receive the first random sequence and the entropy source selection set, and wherein the second circuitry is to generate a second random sequence.

    Hybrid AES-SMS4 hardware accelerator
    10.
    发明授权
    Hybrid AES-SMS4 hardware accelerator 有权

    公开(公告)号：US10218497B2

    公开(公告)日：2019-02-26

    申请号：US15252741

    申请日：2016-08-31

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sudhir Satpathy ,  Sanu Mathew

    IPC: G06F9/30 ,  G09C1/00 ,  H04L9/06

    Abstract: A hybrid AES-SMS4 hardware accelerator is described. A System on Chip implementing a hybrid AES-SMS4 hardware accelerator may include a processor core and a single hardware accelerator coupled to the processor core, the single hardware accelerator to encrypt or decrypt data. The single hardware accelerator may include a first block cipher to encrypt or decrypt the data according to a first encryption algorithm and a second block cipher to encrypt or decrypt the data according to a second encryption algorithm. The accelerator may further include a combined substitution box (Sbox) coupled to the first block cipher and the second block cipher, the combined Sbox comprising logic to perform Galois Field (GF) multiplications and inverse computations, wherein the inverse computations are common to the first block cipher and the second block cipher.

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