公开(公告)号：US20220014400A1

公开(公告)日：2022-01-13

申请号：US17485032

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Yaniv HADAR ,  Golan PERRY ,  Kevan A. LILLIE ,  Kenji HIRATA

IPC: H04L25/03

Abstract: Methods and apparatus to compensate for post-training insertion loss variation. Receiver Physical Layer (PHY) circuitry for each receive lane in a link comprising a chain of equalizer components including a Variable Gain Amplifier (VGA). In conjunction with initial link training, the VGA gain is set based on an initial temperature. During link training, one or more of the equalizer components are adjusted to obtain link convergence, followed by transitioning to a “link up” phase under which data transmission and reception begin. While operating in the link up phase, one or more of the equalizer components are adjusted in response to changes in interconnect insertion loss to maintain operation of the link within a link margin. The method may be implemented in various types of links including but not limited to Ethernet, PCIe, CXL, and UPI links.

公开(公告)号：US20180316524A1

公开(公告)日：2018-11-01

申请号：US15583644

申请日：2017-05-01

Applicant: INTEL CORPORATION

Inventor： Mor M. COHEN ,  Yaniv HADAR ,  Ehud U. SHOOR

IPC: H04L25/03 ,  H04L7/033

CPC classification number: H04L25/03949 ,  H04L7/00 ,  H04L7/033 ,  H04L25/03057 ,  H04L2201/02 ,  H04L2201/04

Abstract: An apparatus is provided which comprises: a data slicer to receive first data sampled by a data clock; an edge slicer to receive second data sampled by an edge clock; and a Least Mean Square (LMS) circuitry coupled to the data and edge slicers, wherein the LSM circuitry is to generate a code to adjust a phase of one of data clock and/or edge clock relative to one another.