公开(公告)号：US06342310B2

公开(公告)日：2002-01-29

申请号：US09770290

申请日：2001-01-29

申请人： Ikurou Hashimoto ,  Kenji Saitou ,  Hiroyuki Takeda ,  Koichi Makii ,  Shunichi Hashimoto ,  Takayuki Yamamoto ,  Masahiro Nomura ,  Kouki Ikeda ,  Masafumi Shimizu

发明人： Ikurou Hashimoto ,  Kenji Saitou ,  Hiroyuki Takeda ,  Koichi Makii ,  Shunichi Hashimoto ,  Takayuki Yamamoto ,  Masahiro Nomura ,  Kouki Ikeda ,  Masafumi Shimizu

IPC分类号： B32B1518

CPC分类号： C23C2/02 ,  C23C2/06 ,  Y10S428/939 ,  Y10T428/12799

摘要： A hot-dip galvanized steel sheet composed of a basis steel sheet containing Si in an amount of 0.05-2.5 mass % and Mn in an amount of 0.2-3 mass % and a hot-dip galvanized zinc layer formed on the surface thereof, wherein said hot-dip galvanized zinc layer is formed in such a way that there is an Si—Mn enriched phase which is found, by observation under a scanning electron microscope or a transmission electron microscope, in the vicinity of the interface in a region no shorter than 50 &mgr;m in the cross section perpendicular to the interface between the basis steel sheet and the hot-dip galvanized zinc layer, said Si—Mn enriched phase containing more than twice as much Si and/or Mn as the basis steel sheet and extending over a length no more than 80% of the length of the interface observed. This hot-dip galvanized steel sheet is free of bare spots even in the case where the basis steel sheet contains Si and Mn in a comparatively large amount and hence is liable to suffering bare spots.

摘要翻译： 一种由含有0.05-2.5质量％的Si和0.2-3质量％的Mn的基础钢板和在其表面上形成的热镀锌锌层构成的热浸镀锌钢板，其中 所述热浸镀锌锌层形成为具有Si-Mn富集相，其通过在扫描型电子显微镜或透射型电子显微镜下观察而在不短的区域的界面附近发现 在与基底钢板和热镀锌锌层之间的界面垂直的截面中，超过50um的所述Si-Mn富集相含有基本钢板的Si和/或Mn的两倍以上并且延伸 长度不超过界面观察长度的80％。 即使在基础钢板中含有较多量的Si和Mn的情况下，该热浸镀锌钢板也无斑点，因此容易产生裸露斑点。

公开(公告)号：US07838961B2

公开(公告)日：2010-11-23

申请号：US11798863

申请日：2007-05-17

申请人： Kenji Saitou ,  Kenichi Hidaka

发明人： Kenji Saitou ,  Kenichi Hidaka

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： A semiconductor device includes a semiconductor substrate having trenches extending thereinto. A trench type insulating film fills the trenches. The trench type insulating film includes a first and second insulating film and is laminated in a portion of the trenches.

摘要翻译： 半导体器件包括具有延伸到其中的沟槽的半导体衬底。 沟槽型绝缘膜填充沟槽。 沟槽型绝缘膜包括第一和第二绝缘膜，并且层叠在沟槽的一部分中。

公开(公告)号：US06498753B2

公开(公告)日：2002-12-24

申请号：US09944792

申请日：2001-08-31

申请人： Kazuhiko Sanada ,  Kenji Saitou ,  Kiyokazu Ishige ,  Hitoshi Nakamura

发明人： Kazuhiko Sanada ,  Kenji Saitou ,  Kiyokazu Ishige ,  Hitoshi Nakamura

IPC分类号： G11C1604

CPC分类号： G11C16/16 ,  Y10S438/942 ,  Y10S438/945

摘要： The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lower erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole.

摘要翻译： 本发明能够完成对半导体存储装置中的组的存储单元的数据擦除，其中对组的存储单元均匀地执行数据擦除，直到所有单元阈值变为低于参考值，并且存储单元具有单元阈值 提供低于下限值的电荷。 当以使得组中预定位置的一些存储单元具有较低擦除速度的方式发生制造误差时，以使得这些存储单元具有高于理想值的擦除速度的方式形成半导体器件。 当组中的一些存储器单元具有较低的擦除速度时，在需要电荷供应的组的大多数存储器单元中执行过度擦除，这增加了整个擦除时间。

公开(公告)号：US4976300A

公开(公告)日：1990-12-11

申请号：US341218

申请日：1989-04-21

申请人： Kenji Takehara ,  Kenji Saitou

发明人： Kenji Takehara ,  Kenji Saitou

IPC分类号： B60C3/04 ,  B60C11/00

CPC分类号： B60C3/04 ,  B60C11/00

摘要： A pneumatic tire in which various tire performances, such as wear resistance, uneven wear resistance, fuel economy and the like are all improved in a good balance is disclosed, whereina first point gap LA defined as the radial distance between a standard first point An on the tire equator on the tread face Tn when the tire is inflated to a standard internal pressure and a 10% first point As on the tire equator on the tread face Ts when the tire is inflated to 10% of said standard internal pressure is smaller than 1.0 mm,a third point gap LC defined as the radial distance between a standard third point Cn on said trade face Tn spaced apart 0.45 times of the tread width TWn from said standard first point An and a 10% third point Cs defined as the intersection of the radial line passing through said standard third point Cn with said tread face Ts is 1.0 mm or larger and smaller than 4.0 mm, andthe ratio LC/LA of said third point gap LC to said first point gap LA is 4.0 or larger.

公开(公告)号：US08014325B2

公开(公告)日：2011-09-06

申请号：US11645512

申请日：2006-12-27

申请人： Haruki Izumikawa ,  Kenji Saitou ,  Keizou Sugiyama

发明人： Haruki Izumikawa ,  Kenji Saitou ,  Keizou Sugiyama

IPC分类号： H04B7/00

CPC分类号： H04L47/10 ,  H04B7/2606 ,  H04L47/14 ,  H04L47/17 ,  H04L47/2441 ,  H04L47/50 ,  H04L47/562 ,  H04W72/1236 ,  H04W72/1278 ,  H04W84/047

摘要： In the P-MP wireless data communication via relay stations, a wireless base station forms a communication schedule between the relay station and the relay station and a communication schedule between the relay station and the subscriber station. For each subscriber station (SS), a connected station, an interference at downloading, an interference at uploading, a burst profile between the BS and the SS, and a burst profile between the RS and the SS are registered in an SS management table of the BS. An interference during downloading is generated by allowing each SS to send an identifier of a BS or an RS acting as an interference to a BS to which the SS is connected. An interference during uploading is generated by allowing the BS to capture ranging fixed at the starting time and the like from an SS being under the control of the RS.

摘要翻译： 在通过中继站的P-MP无线数据通信中，无线基站在中继站和中继站之间形成通信调度，以及中继站与用户站之间的通信调度。 对于每个用户站（SS），连接的站，下载时的干扰，上载干扰，BS和SS之间的突发配置文件以及RS与SS之间的突发配置文件被登记在SS管理表 BS。 通过允许每个SS向BS所连接的BS发送作为干扰的BS或RS的标识符来产生下载期间的干扰。 通过允许BS在RS的控制下的SS的起始时间等捕获测距固定，产生上载期间的干扰。

公开(公告)号：US20050221580A1

公开(公告)日：2005-10-06

申请号：US11090839

申请日：2005-03-25

申请人： Kenji Saitou ,  Kenichi Hidaka

发明人： Kenji Saitou ,  Kenichi Hidaka

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： In a method of manufacturing a semiconductor device with a shallow trench isolation structure, trenches are formed to extend into a semiconductor substrate. Subsequently, a first insulating film is formed to fill the trenches and to cover a whole surface of the semiconductor substrate, and then a first chemical mechanical polishing (CMP) method is carried out to remove the first insulating film such that the first insulating film is left only in the trenches. Subsequently, a second insulating film is formed to fill the trenches and to cover a whole surface of the semiconductor substrate, and a second CMP method is carried out to remove the second insulating film such that the second insulating film is left only in the trenches.

摘要翻译： 在制造具有浅沟槽隔离结构的半导体器件的方法中，形成沟槽以延伸到半导体衬底中。 随后，形成第一绝缘膜以填充沟槽并覆盖半导体衬底的整个表面，然后进行第一化学机械抛光（CMP）方法以去除第一绝缘膜，使得第一绝缘膜为 只留在战壕里。 随后，形成第二绝缘膜以填充沟槽并覆盖半导体衬底的整个表面，并且执行第二CMP方法以去除第二绝缘膜，使得第二绝缘膜仅留在沟槽中。

公开(公告)号：US06330191B2

公开(公告)日：2001-12-11

申请号：US09725633

申请日：2000-11-29

申请人： Kazuhiko Sanada ,  Kenji Saitou ,  Kiyokazu Ishige ,  Hitoshi Nakamura

发明人： Kazuhiko Sanada ,  Kenji Saitou ,  Kiyokazu Ishige ,  Hitoshi Nakamura

IPC分类号： G11C1604

CPC分类号： G11C16/16 ,  Y10S438/942 ,  Y10S438/945

摘要： The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lower erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole. However, when only some memory cells of a group have a higher erase speed, an excessive erase requiring electric charge supply occurs only in some memories and accordingly, it is possible to rapidly complete the data erase in the memory cells of the group.

摘要翻译： 本发明能够完成对半导体存储装置中的组的存储单元的数据擦除，其中对组的存储单元均匀地执行数据擦除，直到所有单元阈值变为低于参考值，并且存储单元具有单元阈值 提供低于下限值的电荷。 当以使得组中预定位置的一些存储单元具有较低擦除速度的方式发生制造误差时，以使得这些存储单元具有高于理想值的擦除速度的方式形成半导体器件。 当组中的一些存储器单元具有较低的擦除速度时，在需要电荷供应的组的大多数存储器单元中执行过度擦除，这增加了整个擦除时间。 然而，当组中只有一些存储单元具有较高的擦除速度时，仅在一些存储器中发生需要电荷供给的过度擦除，因此可以迅速地完成该组的存储单元中的数据擦除。

公开(公告)号：US07449393B2

公开(公告)日：2008-11-11

申请号：US11090839

申请日：2005-03-25

申请人： Kenji Saitou ,  Kenichi Hidaka

发明人： Kenji Saitou ,  Kenichi Hidaka

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： In a method of manufacturing a semiconductor device with a shallow trench isolation structure, trenches are formed to extend into a semiconductor substrate. Subsequently, a first insulating film is formed to fill the trenches and to cover a whole surface of the semiconductor substrate, and then a first chemical mechanical polishing (CMP) method is carried out to remove the first insulating film such that the first insulating film is left only in the trenches. Subsequently, a second insulating film is formed to fill the trenches and to cover a whole surface of the semiconductor substrate, and a second CMP method is carried out to remove the second insulating film such that the second insulating film is left only in the trenches.

摘要翻译： 在制造具有浅沟槽隔离结构的半导体器件的方法中，形成沟槽延伸到半导体衬底中。 随后，形成第一绝缘膜以填充沟槽并覆盖半导体衬底的整个表面，然后进行第一化学机械抛光（CMP）方法以去除第一绝缘膜，使得第一绝缘膜为 只留在战壕里。 随后，形成第二绝缘膜以填充沟槽并覆盖半导体衬底的整个表面，并且执行第二CMP方法以去除第二绝缘膜，使得第二绝缘膜仅留在沟槽中。

公开(公告)号：US20070222026A1

公开(公告)日：2007-09-27

申请号：US11798863

申请日：2007-05-17

申请人： Kenji Saitou ,  Kenichi Hidaka

发明人： Kenji Saitou ,  Kenichi Hidaka

IPC分类号： H01L29/00

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/115

摘要： A semiconductor device includes a semiconductor substrate having trenches extending thereinto. A trench type insulating film fills the trenches. The trench type insulating film includes a first and second insulating film and is laminated in a portion of the trenches.

摘要翻译： 半导体器件包括具有延伸到其中的沟槽的半导体衬底。 沟槽型绝缘膜填充沟槽。 沟槽型绝缘膜包括第一和第二绝缘膜，并且层叠在沟槽的一部分中。

公开(公告)号：US20070147341A1

公开(公告)日：2007-06-28

申请号：US11645512

申请日：2006-12-27

申请人： Haruki Izumikawa ,  Kenji Saitou ,  Keizou Sugiyama

发明人： Haruki Izumikawa ,  Kenji Saitou ,  Keizou Sugiyama

IPC分类号： H04L12/28

CPC分类号： H04L47/10 ,  H04B7/2606 ,  H04L47/14 ,  H04L47/17 ,  H04L47/2441 ,  H04L47/50 ,  H04L47/562 ,  H04W72/1236 ,  H04W72/1278 ,  H04W84/047

摘要： In the P-MP wireless data communication via relay stations, a wireless base station forms a communication schedule between the relay station and the relay station and a communication schedule between the relay station and the subscriber station. For each subscriber station (SS), a connected station, an interference at downloading, an interference at uploading, a burst profile between the BS and the SS, and a burst profile between the RS and the SS are registered in an SS management table of the BS. An interference during downloading is generated by allowing each SS to send an identifier of a BS or an RS acting as an interference to a BS to which the SS is connected. An interference during uploading is generated by allowing the BS to capture ranging fixed at the starting time and the like from an SS being under the control of the RS.

摘要翻译： 在通过中继站的P-MP无线数据通信中，无线基站在中继站和中继站之间形成通信调度，以及中继站与用户站之间的通信调度。 对于每个用户站（SS），连接的站，下载时的干扰，上载干扰，BS和SS之间的突发配置文件以及RS与SS之间的突发配置文件被登记在SS管理表 BS。 通过允许每个SS向BS所连接的BS发送作为干扰的BS或RS的标识符来产生下载期间的干扰。 通过允许BS在RS的控制下的SS的起始时间等捕获测距固定，产生上载期间的干扰。