公开(公告)号：US06498753B2

公开(公告)日：2002-12-24

申请号：US09944792

申请日：2001-08-31

申请人： Kazuhiko Sanada ,  Kenji Saitou ,  Kiyokazu Ishige ,  Hitoshi Nakamura

发明人： Kazuhiko Sanada ,  Kenji Saitou ,  Kiyokazu Ishige ,  Hitoshi Nakamura

IPC分类号： G11C1604

CPC分类号： G11C16/16 ,  Y10S438/942 ,  Y10S438/945

摘要： The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lower erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole.

摘要翻译： 本发明能够完成对半导体存储装置中的组的存储单元的数据擦除，其中对组的存储单元均匀地执行数据擦除，直到所有单元阈值变为低于参考值，并且存储单元具有单元阈值 提供低于下限值的电荷。 当以使得组中预定位置的一些存储单元具有较低擦除速度的方式发生制造误差时，以使得这些存储单元具有高于理想值的擦除速度的方式形成半导体器件。 当组中的一些存储器单元具有较低的擦除速度时，在需要电荷供应的组的大多数存储器单元中执行过度擦除，这增加了整个擦除时间。

公开(公告)号：US06330191B2

公开(公告)日：2001-12-11

申请号：US09725633

申请日：2000-11-29

申请人： Kazuhiko Sanada ,  Kenji Saitou ,  Kiyokazu Ishige ,  Hitoshi Nakamura

发明人： Kazuhiko Sanada ,  Kenji Saitou ,  Kiyokazu Ishige ,  Hitoshi Nakamura

IPC分类号： G11C1604

CPC分类号： G11C16/16 ,  Y10S438/942 ,  Y10S438/945

摘要： The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lower erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole. However, when only some memory cells of a group have a higher erase speed, an excessive erase requiring electric charge supply occurs only in some memories and accordingly, it is possible to rapidly complete the data erase in the memory cells of the group.

摘要翻译： 本发明能够完成对半导体存储装置中的组的存储单元的数据擦除，其中对组的存储单元均匀地执行数据擦除，直到所有单元阈值变为低于参考值，并且存储单元具有单元阈值 提供低于下限值的电荷。 当以使得组中预定位置的一些存储单元具有较低擦除速度的方式发生制造误差时，以使得这些存储单元具有高于理想值的擦除速度的方式形成半导体器件。 当组中的一些存储器单元具有较低的擦除速度时，在需要电荷供应的组的大多数存储器单元中执行过度擦除，这增加了整个擦除时间。 然而，当组中只有一些存储单元具有较高的擦除速度时，仅在一些存储器中发生需要电荷供给的过度擦除，因此可以迅速地完成该组的存储单元中的数据擦除。

公开(公告)号：US06538927B1

公开(公告)日：2003-03-25

申请号：US10183701

申请日：2002-06-26

申请人： Kazuhiko Sanada ,  Kenji Saitou ,  Kiyokazu Ishige ,  Hitoshi Nakamura

发明人： Kazuhiko Sanada ,  Kenji Saitou ,  Kiyokazu Ishige ,  Hitoshi Nakamura

IPC分类号： H01L21339

CPC分类号： G11C16/16 ,  Y10S438/942 ,  Y10S438/945

摘要： The present invention enables to complete a data erase of memory cells of a group in a semiconductor storage device where a data erase is uniformly performed to memory cells of a group until all the cell threshold values become below a reference and memory cells having a cell threshold value below a lower limit are supplied with an electric charge. When a production error occurs in such a way that some memory cells in a predetermined position of a group have a lover erase speed, the semiconductor device is formed in such a way that these memory cells have an erase speed higher than an ideal value. When some memory cells of a group have a lower erase speed, an excessive erase is performed in most memory cells of the group requiring electric charge supply, which increase the erase time as a whole. However, when only some memory cells of a group have a higher erase speed, an excessive erase requiring electric charge supply occurs only in some memories and accordingly, it is possible to rapidly complete the data.

摘要翻译： 本发明能够完成对半导体存储装置中的组的存储单元的数据擦除，其中对组的存储单元均匀地执行数据擦除，直到所有单元阈值变为低于参考值，并且存储单元具有单元阈值 提供低于下限值的电荷。 当以这样的方式发生制造错误时，组中预定位置的某些存储单元具有情人擦除速度，所以半导体器件形成为使得这些存储单元具有高于理想值的擦除速度。 当组中的一些存储器单元具有较低的擦除速度时，在需要电荷供应的组的大多数存储器单元中执行过度擦除，这增加了整个擦除时间。 然而，当组中仅一些存储单元具有较高的擦除速度时，仅在某些存储器中发生需要电荷供应的过度擦除，因此可以快速完成数据。

公开(公告)号：US20120044741A1

公开(公告)日：2012-02-23

申请号：US13067773

申请日：2011-06-24

申请人： Hiromichi Takaoka ,  Kenichi Hidaka ,  Hiroshi Tsuda ,  Kiyokazu Ishige ,  Yoshitaka Kubota ,  Takuji Onuma

发明人： Hiromichi Takaoka ,  Kenichi Hidaka ,  Hiroshi Tsuda ,  Kiyokazu Ishige ,  Yoshitaka Kubota ,  Takuji Onuma

IPC分类号： G11C17/08 ,  H01L21/336 ,  H01L27/088

CPC分类号： H01L27/101 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.

摘要翻译： 第一半导体器件形成在衬底上并且包括第一绝缘膜，第一电极和第一扩散层。 第二半导体器件形成在衬底上并且包括第二绝缘膜，第二电极和第二扩散层。 第二电极耦合到第一电极。 控制晶体管允许源极和漏极中的一个耦合到第一电极和第二电极，允许源极和漏极中的另一个耦合到位线，并且允许栅电极耦合到 一个字线。 第一电位控制线耦合到第一扩散层并控制第一扩散层的电位。 第二电位控制线耦合到第二扩散层并控制第二扩散层的电位。

公开(公告)号：US06392268B2

公开(公告)日：2002-05-21

申请号：US09154982

申请日：1998-09-17

申请人： Kiyokazu Ishige

发明人： Kiyokazu Ishige

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7881

摘要： The present invention prevents a charge-up during a wiring layer etching in a nonvolatile semiconductor storage apparatus having a floating gate and a control gate to which both of positive and negative voltages are applied during a memory cell operation. On a semiconductor substrate 51 of a first conductive type, a first well 52 of a second conductive type is formed to oppose to the first conductive type. In the first well 52, a second well 53 of the first conductive type is formed. On a main surface of the second well 53 is formed a composite gate 8 consisting of a first gate insulation film 4, a floating gate 5, a second gate insulation film 6, and a control gate 7 which are successively layered. On a surface of the second well 53 are formed by way of ion implantation, a source, a drain, and a charge-up preventing element diffusion layer 18 of the second conductive type.

摘要翻译： 本发明防止了在具有浮置栅极和控制栅极的非易失性半导体存储装置中进行布线层蚀刻期间的充电，在存储单元操作期间施加正电压和负电压两者。在半导体基板51中， 第一导电类型，第二导电类型的第一阱52形成为与第一导电类型相对。 在第一阱52中形成第一导电类型的第二阱53。 在第二阱53的主表面上形成由第一栅极绝缘膜4，浮置栅极5，第二栅极绝缘膜6和控制栅极7构成的复合栅极8，它们依次层叠。 在第二阱53的表面上，通过离子注入形成第二导电类型的源极，漏极和电荷防止元件扩散层18。

公开(公告)号：US5648285A

公开(公告)日：1997-07-15

申请号：US533966

申请日：1995-09-26

申请人： Kiyokazu Ishige

发明人： Kiyokazu Ishige

IPC分类号： H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  Y10S148/157

摘要： In a method for manufacturing a semiconductor memory device including a plurality of field areas, a plurality of electrode areas, a plurality of source areas and drain areas sunrounded by the field areas and the electrode areas, before forming field insulating layers for isolating the source and drain regions, impurities are introduced into the field areas between the source regions, to create an additional source region below the field insulating layer for isolating the source regions. The additional source regions are linked between the source regions.

摘要翻译： 在制造半导体存储器件的方法中，在形成用于隔离源极的场绝缘层之前，包括多个场区域，多个电极区域，由场区域和电极区域包围的多个源极区域和漏极区域，以及 漏极区域，杂质被引入到源极区域之间的场区域中，以在场绝缘层下方产生用于隔离源极区域的附加源极区域。 附加源区域在源区域之间连接。

公开(公告)号：US08675385B2

公开(公告)日：2014-03-18

申请号：US13067773

申请日：2011-06-24

申请人： Hiromichi Takaoka ,  Kenichi Hidaka ,  Hiroshi Tsuda ,  Kiyokazu Ishige ,  Yoshitaka Kubota ,  Takuji Onuma

发明人： Hiromichi Takaoka ,  Kenichi Hidaka ,  Hiroshi Tsuda ,  Kiyokazu Ishige ,  Yoshitaka Kubota ,  Takuji Onuma

IPC分类号： G11C17/08

CPC分类号： H01L27/101 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.

摘要翻译： 第一半导体器件形成在衬底上并且包括第一绝缘膜，第一电极和第一扩散层。 第二半导体器件形成在衬底上并且包括第二绝缘膜，第二电极和第二扩散层。 第二电极耦合到第一电极。 控制晶体管允许源极和漏极中的一个耦合到第一电极和第二电极，允许源极和漏极中的另一个耦合到位线，并且允许栅电极耦合到 一个字线。 第一电位控制线耦合到第一扩散层并控制第一扩散层的电位。 第二电位控制线耦合到第二扩散层并控制第二扩散层的电位。

公开(公告)号：US08530949B2

公开(公告)日：2013-09-10

申请号：US13250516

申请日：2011-09-30

申请人： Takuji Onuma ,  Kenichi Hidaka ,  Hiromichi Takaoka ,  Yoshitaka Kubota ,  Hiroshi Tsuda ,  Kiyokazu Ishige

发明人： Takuji Onuma ,  Kenichi Hidaka ,  Hiromichi Takaoka ,  Yoshitaka Kubota ,  Hiroshi Tsuda ,  Kiyokazu Ishige

IPC分类号： H01L29/76 ,  H01L29/78

CPC分类号： H01L27/11206 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact.

摘要翻译： 即使利用确定电极中是否有电荷的方法，内部书面信息也无法分析的反熔丝。 反熔丝包括栅极绝缘膜，栅电极和第一扩散层。 第二扩散层通过器件隔离膜从第一扩散层隔离，并且是与第一扩散层相同的导电类型。 栅极布线形成为与栅极电极一体化的部件，并且在器件隔离膜上延伸。 常见的接触将栅极布线耦合到第二扩散层。 栅电极由掺杂有与第一扩散层相同导电类型的杂质的多晶硅等半导体材料构成。 第二扩散层仅耦合到公共接触。

公开(公告)号：US06677196B2

公开(公告)日：2004-01-13

申请号：US10303918

申请日：2002-11-26

申请人： Kiyokazu Ishige

发明人： Kiyokazu Ishige

IPC分类号： H01L218242

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11531

摘要： A semiconductor memory device is provided, which makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric. This device comprises a memory cell section including floating-gate type transistors and a capacitor section including capacitors. The memory cell section and the capacitor section are formed on a semiconductor substrate. Each of the transistors has a first gate dielectric, a floating gate, a second gate dielectric, and a control gate. Each of the capacitors has a lower electrode, a capacitor dielectric, and an upper electrode. A first part of the capacitors is/are designed to be applied with a first voltage and a second part thereof is/are applied with a second voltage on operation, where the first voltage is lower than the second voltage. Each of the first part of the capacitors has a recess formed on the lower electrode, thereby increasing its capacitance.

摘要翻译： 提供一种半导体存储器件，这使得可以增加电容器部分中的电容器的电容，而不降低电容器电介质的耐受电压。 该装置包括具有浮栅型晶体管的存储单元部分和包括电容器的电容器部分。 存储单元部分和电容器部分形成在半导体衬底上。 每个晶体管具有第一栅极电介质，浮置栅极，第二栅极电介质和控制栅极。 每个电容器具有下电极，电容器电介质和上电极。 电容器的第一部分被设计成施加第一电压，并且其第二部分被施加第二电压操作，其中第一电压低于第二电压。 电容器的第一部分中的每一个具有形成在下电极上的凹部，从而增加其电容。

公开(公告)号：US06515326B2

公开(公告)日：2003-02-04

申请号：US09887072

申请日：2001-06-25

申请人： Kiyokazu Ishige

发明人： Kiyokazu Ishige

IPC分类号： H01L218247

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11531

摘要： A semiconductor memory device is provided, which makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric. This device comprises a memory cell section including floating-gate type transistors and a capacitor section including capacitors. The memory cell section and the capacitor section are formed on a semiconductor substrate. Each of the transistors has a first gate dielectric, a floating gate, a second gage dielectric, and a control gate. Each of the capacitors has a lower electrode, a capacitor dielectric, and an upper electrode. A first part of the capacitors is/are designed to be applied with a first voltage and a second part thereof is/are applied with a second voltage on operation, where the first voltage is lower than the second voltage. Each of the first part of the capacitors has a recess formed on the lower electrode, thereby increasing its capacitance.

摘要翻译： 提供一种半导体存储器件，这使得可以增加电容器部分中的电容器的电容，而不降低电容器电介质的耐受电压。 该装置包括具有浮栅型晶体管的存储单元部分和包括电容器的电容器部分。 存储单元部分和电容器部分形成在半导体衬底上。 每个晶体管具有第一栅极电介质，浮置栅极，第二量规电介质和控制栅极。 每个电容器具有下电极，电容器电介质和上电极。 电容器的第一部分被设计成施加第一电压，并且其第二部分被施加第二电压操作，其中第一电压低于第二电压。 电容器的第一部分中的每一个具有形成在下电极上的凹部，从而增加其电容。