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    METHOD FOR FABRICATING LIGHT EMITTING DIODE CHIP
    5.
    发明申请
    METHOD FOR FABRICATING LIGHT EMITTING DIODE CHIP 失效
    用于制造发光二极管芯片的方法

    公开(公告)号：US20120171791A1

    公开(公告)日：2012-07-05

    申请号：US13207439

    申请日：2011-08-11

    申请人： PO-MIN TU ,  SHIH-CHENG HUANG

    发明人： PO-MIN TU ,  SHIH-CHENG HUANG

    IPC分类号： H01L21/78

    CPC分类号： H01L33/20 ,  H01L33/007 ,  H01L33/0095 ,  Y10S438/945

    摘要： A method for fabricating an LED chip is provided. Firstly, a SiO2 pattern layer is formed on a top surface of a substrate. Then, lighting structures are grown on a portion of the top surface of substrate without the SiO2 pattern layer thereon. Thereafter, the SiO2 pattern layer is removed by wet etching to form spaces between bottoms of the lighting structures and substrate. An etching solution is used to permeate into the spaces and etch the lighting structures from the bottoms thereof, whereby the lighting structures each with a trapezoid shape is formed. Sidewalls of each of the lighting structures are inclined inwardly along a top-to-bottom direction.

    摘要翻译： 提供一种制造LED芯片的方法。 首先，在基板的上表面上形成SiO 2图形层。 然后，在衬底的顶表面的一部分上生长照明结构，而不在其上形成SiO 2图案层。 此后，通过湿蚀刻去除SiO 2图案层，以在照明结构和基板的底部之间形成空间。 使用蚀刻溶液渗透到空间中并从其底部蚀刻照明结构，由此形成各自具有梯形形状的照明结构。 每个照明结构的侧壁沿着顶部到底部的方向向内倾斜。

    CMOS imager with integrated circuitry
    9.
    发明授权
    CMOS imager with integrated circuitry 有权
    CMOS成像器集成电路

    公开(公告)号：US08089542B2

    公开(公告)日：2012-01-03

    申请号：US13118066

    申请日：2011-05-27

    申请人： Christophe J. Chevallier

    发明人： Christophe J. Chevallier

    IPC分类号： H04N5/225 ,  H04N5/76 ,  H04N3/14

    CPC分类号： H04N5/772 ,  H04N5/335 ,  H04N5/907 ,  H04N9/8047 ,  Y10S438/945

    摘要： A CMOS imager is integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. Integrating a CMOS imager and peripheral circuitry allows for a single chip image sensing device.

    摘要翻译： CMOS成像器与逻辑和支持电路集成在单个基板上，用于解码和处理由CMOS成像器接收的光学信息。 集成CMOS成像器和外围电路允许单片图像感测设备。

    Semiconductor device and method of producing same
    10.
    发明授权
    Semiconductor device and method of producing same 有权
    半导体装置及其制造方法

    公开(公告)号：US07718498B2

    公开(公告)日：2010-05-18

    申请号：US11432264

    申请日：2006-05-11

    申请人： Kazuichiro Itonaga

    发明人： Kazuichiro Itonaga

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7838 ,  H04N5/3741 ,  Y10S438/945

    摘要： A semiconductor device suitable for a source-follower circuit, provided with a gate electrode formed on a semiconductor substrate via a gate insulation film, a first conductivity type layer formed in the semiconductor substrate under a conductive portion of the gate electrode and containing a first conductivity type impurity, first source/drain regions of the first conductivity type impurity formed in the semiconductor substrate and extended from edge portions of the gate electrode, and second source/drain regions having a first conductivity type impurity concentration lower than that in the first source/drain regions and formed adjoining the gate insulation film and the first source/drain regions in the semiconductor substrate so as to overlap portions of the conductive portion of the gate electrode.

    摘要翻译： 一种适用于源极跟随器电路的半导体器件，其设置有通过栅极绝缘膜形成在半导体衬底上的栅极电极，形成在半导体衬底中的栅极电极的导电部分下方并且包含第一导电性的第一导电型层 形成在半导体衬底中并从栅电极的边缘部分延伸的第一导电类型杂质的第一源极/漏极区域，以及具有比第一源极/漏极区域低的第一导电类型杂质浓度的第二源极/ 漏区，并且与半导体衬底中的栅极绝缘膜和第一源极/漏极区相邻地形成，以与栅电极的导电部分重叠。