公开(公告)号：US20180205382A1

公开(公告)日：2018-07-19

申请号：US15408655

申请日：2017-01-18

Applicant: Integrated Device Technology, Inc.

Inventor： Hui Li ,  Teck-Chuan Ng ,  Stephen E. Aycock

IPC: H03K21/02 ,  H03M3/00

CPC classification number: H03K21/02 ,  H03M3/456

Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal in a period determined by (i) an output clock signal and (ii) a second code. The second code may be variable. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal (i) in response to the third code and (ii) within an accuracy determined the second code.

公开(公告)号：US10483982B2

公开(公告)日：2019-11-19

申请号：US16139340

申请日：2018-09-24

Applicant: Integrated Device Technology, Inc.

Inventor： Hui Li ,  Teck-Chuan Ng ,  Stephen E. Aycock

IPC: H03L7/18 ,  H03L1/00 ,  H03L7/183 ,  H03K21/02 ,  H03M3/00

Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal during a period. The period may be determined by an output clock signal and a second code. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal in response to the third code. An accuracy of a frequency of the output clock signal may be determined by a current value of the second code.

公开(公告)号：US20190028105A1

公开(公告)日：2019-01-24

申请号：US16139340

申请日：2018-09-24

Applicant: Integrated Device Technology, Inc.

Inventor： Hui Li ,  Teck-Chuan Ng ,  Stephen E. Aycock

IPC: H03K21/02 ,  H03M3/00

Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal during a period. The period may be determined by an output clock signal and a second code. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal in response to the third code. An accuracy of a frequency of the output clock signal may be determined by a current value of the second code.

公开(公告)号：US10084457B2

公开(公告)日：2018-09-25

申请号：US15408655

申请日：2017-01-18

Applicant: Integrated Device Technology, Inc.

Inventor： Hui Li ,  Teck-Chuan Ng ,  Stephen E. Aycock

IPC: H03L7/18 ,  H03L1/00 ,  H03L7/183 ,  H03K21/02 ,  H03M3/00

CPC classification number: H03K21/02 ,  H03M3/39 ,  H03M3/456

Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal in a period determined by (i) an output clock signal and (ii) a second code. The second code may be variable. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal (i) in response to the third code and (ii) within an accuracy determined the second code.