公开(公告)号：US11768564B2

公开(公告)日：2023-09-26

申请号：US17202862

申请日：2021-03-16

Applicant: Cypress Semiconductor Corporation

Inventor： Viktor Kremin ,  Oleksandr Pirogov ,  Vadym Grygorenko ,  Jens Weber

IPC: G06F3/044 ,  G01R27/26 ,  H03K17/96 ,  H03M3/00 ,  G06F3/041

CPC classification number: G06F3/044 ,  G01R27/2605 ,  G06F3/0418 ,  G06F3/04166 ,  H03K17/962 ,  H03M3/39 ,  G06F2203/04108 ,  H03K2217/96074

Abstract: An apparatus includes a global baseliner circuit coupled with sensing channels of a sensing device. The global baseliner circuit has a signal generator to generate a rectified sinusoidal signal and a square wave having a frequency matching that of an excitation sinusoidal signal, and is to use the square wave to modulate the excitation sinusoidal signal provided at an output of the global baseliner circuit. A channel baseliner circuit is coupled between the global baseliner circuit and a sensing channel and that includes a switched capacitor coupled between the output of the global baseliner circuit and the sensing channel; a sigma-delta modulator coupled with the signal generator and to generate, from the rectified sinusoidal signal, a density-modulated bit stream; and a pair of AND gates to use the density-modulated bit stream and non-overlapping clock signals to generate outputs including density-modulated clock signals sent to switches of the switched capacitor.

公开(公告)号：US20180176695A1

公开(公告)日：2018-06-21

申请号：US15847347

申请日：2017-12-19

Applicant: WIDEX A/S

Inventor： Niels Ole KNUDSEN

IPC: H04R25/00 ,  H03M3/00

CPC classification number: H04R25/453 ,  H03M3/39 ,  H03M3/464 ,  H04R1/04 ,  H04R25/502 ,  H04R25/505 ,  H04R25/60 ,  H04R25/604

Abstract: A hearing assistive device having an input transducer (18) for picking up sound from the environment, a digital signal processor (27) for alleviating a hearing loss of a specific user by compensating an audio signal according to the users hearing deficit, and an output transducer (29) for reproducing the compensated audio signal. The hearing assistive device further includes an integrated circuit component (40) having at least one analog-to-digital converter adapted for receiving an audio input signal from a microphone and providing a data output for signal processing. The at least one analog-to-digital converter includes an AC filter (50) preventing audible signal losses towards the microphone, and the AC filter (50) is provided with all components integrated in the integrated circuit component (40).

公开(公告)号：US20180048327A1

公开(公告)日：2018-02-15

申请号：US15554970

申请日：2015-04-01

Applicant: TDK Corporation

Inventor： Niels Marker-Villumsen

IPC: H03M3/00

CPC classification number: H03M3/382 ,  H03M1/004 ,  H03M3/39 ,  H03M3/422 ,  H03M3/458

Abstract: A sigma-delta modulator arrangement includes a continuous-time sigma-delta modulator with at least one modulator stage, a digital integrator and a given number of switches. The switches are arranged and configured to convert the continuous-time sigma-delta modulator into a first order incremental sigma-delta analog-to-digital converter comprising the digital integrator. At least a first modulator stage of the continuous-time sigma-delta-modulator, which is coupled with an input of the continuous-time sigma-delta modulator, includes at least one tuning element for adjusting an input signal and/or a feedback signal which are supplied to the first modulator stage.

公开(公告)号：US09813077B2

公开(公告)日：2017-11-07

申请号：US15323038

申请日：2015-06-30

Applicant: Indice Semiconductor Inc.

Inventor： James Hamond ,  Robert D. Batten

IPC: H03M3/00

CPC classification number: H03M3/50 ,  H03M3/32 ,  H03M3/37 ,  H03M3/39 ,  H03M3/402 ,  H03M3/43 ,  H03M3/458

Abstract: Asynchronous electrical circuitry produces a stationary carrier signal and encodes a system input signal amplitude into output signal time-sequence information by establishing at a digitizer an operating point value as an average amplitude of the system input signal. It applies to the digitizer a multicomponent digitizer-input signal corresponding to a sum of a passband signal component and a feedback signal component to produce a pulse-width modulated digitizer output signal representing the system input signal. An asynchronous time delay is introduced to produce the pulse-width modulated system output signal. The circuitry performs digital-to-analog conversion (DAC) to the pulse-width modulated system output signal to produce a DAC output signal. The DAC output signal or its summation with the passband signal component is integrated to produce the feedback signal component. Additional, multiple-order embodiments include sequential feedback paths or carrier-shaping functions.

公开(公告)号：US09628104B2

公开(公告)日：2017-04-18

申请号：US14657323

申请日：2015-03-13

Applicant: Rosemount Inc.

Inventor： Rongtai Wang ,  John Paul Schulte

IPC: G01L9/12 ,  H03M3/00 ,  G01D5/24

CPC classification number: H03M3/39 ,  G01D5/24 ,  G01L9/0072 ,  G01L9/0075 ,  G01L9/12 ,  H03M3/356 ,  H03M3/376 ,  H03M3/494

Abstract: A single plate capacitance sensor includes a sensor capacitor and a reference capacitor that share common plate. A capacitance-to-digital sigma delta modulator provides separate sensor excitation and reference excitation signals to the sensor capacitor and the reference capacitor to provide high resolution detection. Programmable ratio-metric excitation voltages and adaptive excitation voltage sources can be used to enhance modulator performance.

公开(公告)号：US09571931B1

公开(公告)日：2017-02-14

申请号：US14247987

申请日：2014-04-08

Applicant: Cirrus Logic, Inc.

Inventor： John L. Melanson ,  John C. Tucker

IPC: H04R3/02 ,  H04R3/00 ,  H04R29/00 ,  H04R19/04

CPC classification number: H04R3/02 ,  H03F1/26 ,  H03F3/16 ,  H03F2200/372 ,  H03M3/00 ,  H03M3/39 ,  H03M3/424 ,  H03M3/458 ,  H03M3/50 ,  H03M7/3026 ,  H03M7/3028 ,  H04R3/00 ,  H04R3/002 ,  H04R3/007 ,  H04R19/04 ,  H04R29/001

Abstract: To correct for non-linearities in the response of a microphone as a function of sound pressure level incident upon the microphone, a displacement non-linearity function is applied to the signal path of the microphone, wherein the displacement non-linearity function is a function of the digital audio output signal and has a response modeling non-linearities of the displacement as a function of a sound pressure level incident upon the microphone.

Abstract translation: 为了校正麦克风的响应中的非线性作为入射到麦克风的声压级的函数，位移非线性函数被施加到麦克风的信号路径，其中位移非线性函数是函数 的数字音频输出信号，并且具有作为入射到麦克风的声压级的函数的位移的非线性的响应建模。

公开(公告)号：US20160308552A1

公开(公告)日：2016-10-20

申请号：US15132716

申请日：2016-04-19

Applicant: Benjamin H. Ashmore, JR.

Inventor： Benjamin H. Ashmore, JR.

IPC: H03M3/00

CPC classification number: H03M3/382 ,  H03M3/39 ,  H03M3/43 ,  H03M3/456

Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.

公开(公告)号：US09419562B1

公开(公告)日：2016-08-16

申请号：US14248054

申请日：2014-04-08

Applicant: Cirrus Logic, Inc.

Inventor： John L. Melanson ,  John C. Tucker

IPC: H03F1/02 ,  H03F1/26 ,  H03F3/16

CPC classification number: H04R3/02 ,  H03F1/26 ,  H03F3/16 ,  H03F2200/372 ,  H03M3/00 ,  H03M3/39 ,  H03M3/424 ,  H03M3/458 ,  H03M3/50 ,  H03M7/3026 ,  H03M7/3028 ,  H04R3/00 ,  H04R3/002 ,  H04R3/007 ,  H04R19/04 ,  H04R29/001

Abstract: An amplifier may include a plurality of stages, wherein each stage may have an amplifier stage output configured to generate an amplifier output signal and a transistor coupled at its gate terminal to the amplifier input and to the gate terminals of the transistors of the other amplifier stages. Each stage may be configured to periodically and cyclically operate in an amplifier mode in which the amplifier stage generates at its corresponding amplifier stage output a power-amplified version of a signal received at the amplifier input and a in reset mode in which the transistor of the stage operating in the reset mode has an electrical property thereof reset. At any given time, at least one amplifier stage is operating in the amplifier mode. The amplifier may be configured to output as an output signal one of the amplifier output signals corresponding to an amplifier stage operating in the amplifier mode.

Abstract translation: 放大器可以包括多个级，其中每个级可以具有被配置为产生放大器输出信号的放大器级输出和在其栅极端耦合到放大器输入端和耦合到其它放大器级的晶体管的栅极端子的晶体管 。 每个级可以被配置为在放大器模式中周期性地和周期性地工作，其中放大器级在其相应的放大级产生输出在放大器输入处接收的信号的功率放大形式，在复位模式中， 在复位模式下工作的电平具有电性能的复位。 在任何给定时间，至少一个放大器级在放大器模式下工作。 放大器可以被配置为输出对应于以放大器模式工作的放大器级的放大器输出信号之一作为输出信号。

公开(公告)号：US09379734B2

公开(公告)日：2016-06-28

申请号：US14939679

申请日：2015-11-12

Applicant: ZENTRUM MIKROELEKTRONIK DRESDEN AG

Inventor： Raik Richter ,  Marko Mailand

IPC: H03M3/00

CPC classification number: H03M3/464 ,  H03M3/356 ,  H03M3/39 ,  H03M3/484 ,  H03M3/488

Abstract: A method and arrangement for setting an effective resolution of an output signal in an incremental delta-sigma analog-to-digital conversion by an incremental delta-sigma analog-to-digital converter, includes feeding a difference between an input signal and a reference voltage signal formed in a feedback branch to a first integrator. Safeguarding the stability of multi-stage incremental delta-sigma analog-to-digital converters for large input signal ranges and not requiring direct damping of the input signal, such that a direct SNR impairment with regard to the ADC-inherent noise sources can be avoided, is achieved by a virtual reference voltage in the feedback branch of the incremental delta-sigma analog-to-digital converter. The reference voltage signal is adapted to a changing input signal range by a settable reference capacitance and a clock cycle number dependent thereon is set.

Abstract translation: 用于通过增量Δ-Σ模数转换器设置增量Δ-Σ模数转换中的输出信号的有效分辨率的方法和装置包括馈送输入信号和参考电压之间的差 在第一积分器的反馈分支中形成的信号。 保护多级增量Δ-Σ模数转换器对于大输入信号范围的稳定性，不需要输入信号的直接阻尼，从而可以避免相对于ADC固有噪声源的直接SNR损害 ，通过增量Δ-Σ模数转换器的反馈支路中的虚拟参考电压来实现。 参考电压信号适应于可变参考电容的改变的输入信号范围，并且依赖于其的时钟周期数被设置。

公开(公告)号：US20160182068A1

公开(公告)日：2016-06-23

申请号：US14910129

申请日：2014-08-07

Applicant: POSTECH ACDEMY-INDUSTRY FOUNDATION

Inventor： Jae Yoon SIM ,  Seung Hwan HONG

IPC: H03L7/197 ,  H03M3/00 ,  H03L7/095 ,  G04F10/00 ,  H03L7/083 ,  H03L7/099

CPC classification number: H03L7/1974 ,  G04F10/005 ,  H03L7/083 ,  H03L7/095 ,  H03L7/0992 ,  H03L7/0995 ,  H03L7/1976 ,  H03L7/23 ,  H03L2207/50 ,  H03M3/39

Abstract: The present invention relates to a technique capable of implementing a frequency synthesizer circuit separated into a frequency synthesizer circuit part and an injection locked PLL circuit part and sequentially performing a frequency synthesizer lock operation and an injection lock operation to implement fast frequency and phase locking. The present invention comprises: a frequency synthesizer configured to perform a frequency and phase lock operation according to fractional number information and a first reference cock signal supplied from outside and thereby output a reset signal and a second reference clock signal; and an injection locked PLL configured to start a frequency lock operation after being reset by the reset signal inputted when the frequency synthesizer is frequency-locked, receive the second reference clock signal as a reference clock, multiply the second reference clock signal by an integer multiple of target frequency, and output an output clock signal.

Abstract translation: 本发明涉及一种能够实现分频为频率合成器电路部分的频率合成器电路和注入锁定PLL电路部分，并且顺序执行频率合成器锁定操作和注入锁定操作以实现快速频率和相位锁定的技术。 本发明包括：频率合成器，被配置为根据分数信息和从外部提供的第一参考旋转信号执行频率和相位锁定操作，从而输出复位信号和第二参考时钟信号; 以及注入锁定PLL，被配置为在由频率合成器频率锁定后输入的复位信号复位之后开始频率锁定操作，接收第二参考时钟信号作为参考时钟，将第二参考时钟信号乘以整数倍 的目标频率，并输出一个输出时钟信号。