公开(公告)号：US20240291416A1

公开(公告)日：2024-08-29

申请号：US18644996

申请日：2024-04-24

Applicant: Tula eTechnology, Inc.

Inventor： Adya S. TRIPATHI

IPC: H02P27/08 ,  H03M3/00

CPC classification number: H02P27/08 ,  H02P27/085 ,  H03M3/438 ,  H03M3/456

Abstract: Methods, controllers and electric machine systems are described that facilitate pulsed control of electric machines (e.g., electric motors and generators) to improve the machine's energy conversion efficiency. Under selected operating conditions, the electric machine is intermittently driven (pulsed). The pulsed operation causes the output of the electric machine to alternate between a first output level and an off state. The output levels are selected such that the electric machine has a higher energy conversion efficiency during the pulsed operation than the electric machine would have when operated at a third output level that would be required to drive the electric machine in a continuous manner to deliver the desired output. In some embodiments, the power converter it turned off during at least portions of the time that the electric machine is pulsed off.

公开(公告)号：US11962331B2

公开(公告)日：2024-04-16

申请号：US17814978

申请日：2022-07-26

Applicant: NXP B.V.

Inventor： Robert van Veldhoven

IPC: H03M3/00

CPC classification number: H03M3/434 ,  H03M3/456 ,  H03M3/49

Abstract: A sigma-delta ADC is described including a passive filter with an input coupled to the ADC input and a filter output. A gain stage has an input connected to the filter output. A quantiser has an input connected to the gain stage output and a quantiser output. The passive filter includes a first filter resistor between the filter input and the filter output and a filter capacitor having first terminal coupled to the filter output. A feedback resistor is coupled between the quantiser output and the filter output and receives a negative of the value of the output to provide negative feedback to the filter output. The gain stage has a capacitor and resistor in series, and a gain element connected to the gain stage input and an output connected to the gain stage output. One terminal of the gain stage capacitor is connected to the gain element output.

公开(公告)号：US11740136B2

公开(公告)日：2023-08-29

申请号：US17011723

申请日：2020-09-03

Applicant: STMicroelectronics S.r.l.

Inventor： Michele Vaiana ,  Paolo Pesenti ,  Mario Chiricosta ,  Calogero Marco Ippolito ,  Mario Maiore

IPC: G01K3/14 ,  H03H17/02 ,  G01K7/02 ,  H03M3/00 ,  H03K19/003 ,  H03K19/018

CPC classification number: G01K3/14 ,  G01K7/02 ,  G01K7/021 ,  H03H17/02 ,  G01K2219/00 ,  H03K19/00307 ,  H03K19/01825 ,  H03M3/43 ,  H03M3/456 ,  H03M3/458

Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.

公开(公告)号：US20190074843A1

公开(公告)日：2019-03-07

申请号：US16179405

申请日：2018-11-02

Applicant: SHENZHEN GOODIX TECHNOLOGY CO., LTD.

Inventor： YA-NAN WEN ,  YINGSI LIANG

IPC: H03M1/08 ,  H03M3/00

CPC classification number: H03M1/08 ,  H03M3/424 ,  H03M3/45 ,  H03M3/452 ,  H03M3/454 ,  H03M3/456 ,  H03M3/46 ,  H03M3/462 ,  H03M7/3026

Abstract: The present disclosure provides a converting module formed in a first die. The first die is coupled to a bus having a bus bit width. The converting module includes an analog-to-digital converter, configured to generate a first digital signal having a first bit width different from the bus bit width; and a sigma-delta modulator, coupled to the analog-to-digital converter, and configured to generate a second digital signal according to the first digital signal. The second digital signal has a bit width equal to the bus bit width. The sigma-delta modulator includes a filter and a quantizer. The number of bits outputted by the quantizer is equal to the bus bit width.

公开(公告)号：US09641193B2

公开(公告)日：2017-05-02

申请号：US14849280

申请日：2015-09-09

Applicant: Micron Technology, Inc.

Inventor： Russel J. Baker

IPC: G11C7/06 ,  H03M3/00 ,  G11C7/02 ,  G11C7/04 ,  G11C7/16 ,  G11C8/08 ,  G11C8/10 ,  G11C11/56 ,  G11C13/00 ,  G11C27/00 ,  H04N5/378 ,  G11C16/28

CPC classification number: H03M3/456 ,  G11C7/02 ,  G11C7/04 ,  G11C7/06 ,  G11C7/065 ,  G11C7/16 ,  G11C8/08 ,  G11C8/10 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C16/28 ,  G11C27/005 ,  G11C2013/0054 ,  G11C2211/5645 ,  H03M3/39 ,  H03M3/43 ,  H04N5/378

Abstract: Methods, systems and devices are disclosed, such as an electronic device that includes a plurality of data locations and a delta-sigma modulator. In some embodiments, the delta-sigma modulator includes a preamplifier coupled to the data locations and a latch coupled to the preamplifier.

公开(公告)号：US20170111056A1

公开(公告)日：2017-04-20

申请号：US14885047

申请日：2015-10-16

Applicant: Sony Semiconductor Solutions Corporation

Inventor： Vadim Tkachev

IPC: H03M3/00 ,  H04N5/225 ,  H04N5/378

CPC classification number: H03M3/486 ,  H03M3/372 ,  H03M3/43 ,  H03M3/45 ,  H03M3/454 ,  H03M3/456 ,  H03M3/462 ,  H03M3/464 ,  H03M3/496 ,  H04N5/2253 ,  H04N5/378

Abstract: A current mode sigma-delta modulator comprises an input node; a comparator that compares a voltage of the input node to a reference voltage and outputs a comparison result; an integrating capacitor connected to an input of the comparator; and a switched capacitor circuit connected at a first end to the input node, the input of the comparator, and the integrating capacitor, and connected at a second end to an output of the comparator. The current mode sigma-delta modulator is a component of an analog-to-digital converter.

公开(公告)号：US20160043733A1

公开(公告)日：2016-02-11

申请号：US14819767

申请日：2015-08-06

Applicant: DENSO CORPORATION

Inventor： Tomohiro NEZUKA

IPC: H03M3/00

CPC classification number: H03M3/368 ,  H03M1/00 ,  H03M1/12 ,  H03M3/30 ,  H03M3/43 ,  H03M3/456 ,  H03M3/464

Abstract: An A/D converter includes a delta-sigma processing circuit for A/D conversion by delta-sigma modulation, and a cyclic processing circuit for A/D conversion by cyclic processing of amplification of a residue generated in the A/D conversion. The A/D converter further includes a quantization part for outputting a quantized value of quantized output of the delta-sigma processing circuit and a quantized output of the cyclic processing circuit, and a control circuit for generating an A/D conversion result and switching over a reference voltage based on the quantized value. The delta-sigma processing circuit and the cyclic processing circuit include a sampling capacitor, an integration capacitor and a capacitive D/A converter, which includes a DAC capacitor and add and subtract a charge corresponding to a reference voltage to and from a residue of quantization. The sampling capacitor, the DAC capacitor and the integration capacitor are provided as electrically separate capacitors.

Abstract translation: A / D转换器包括用于通过Δ-Σ调制进行A / D转换的Δ-sigma处理电路和用于通过A / D转换中产生的残余物的放大的循环处理进行A / D转换的循环处理电路。 A / D转换器还包括用于输出Δ-Σ处理电路的量化输出的量化值和循环处理电路的量化输出的量化部分，以及用于产生A / D转换结果和切换的控制电路 基于量化值的参考电压。 Δ-Σ处理电路和循环处理电路包括采样电容器，积分电容器和电容性D / A转换器，其包括DAC电容器，并将与参考电压相对应的电荷加到量化残余物中 。 采样电容器，DAC电容器和积分电容器作为电气分离电容器提供。

公开(公告)号：US08797455B2

公开(公告)日：2014-08-05

申请号：US13549737

申请日：2012-07-16

Applicant: Ja Seung Gou ,  Oh Kyong Kwon ,  Min Seok Shin ,  Min Kyu Kim

Inventor： Ja Seung Gou ,  Oh Kyong Kwon ,  Min Seok Shin ,  Min Kyu Kim

IPC: H04N5/225

CPC classification number: H03M1/145 ,  H03M1/1225 ,  H03M1/403 ,  H03M3/43 ,  H03M3/456 ,  H04N5/378

Abstract: The analog-to-digital converter includes a signal processing unit generating an operational amplifier output voltage in response to an input voltage and a DAC output voltage in a first period and generating the operational amplifier output voltage in response to a feedbacked operational amplifier output voltage and the DAC output voltage in a second period; a control unit generating a DAC control signal by comparing the operational amplifier output voltage with a first reference voltage to obtain high order M-bits of data in the first period, and generating the DAC control signal by comparing the operational amplifier output voltage with second and third reference voltages to obtain low order N-bits of data in the second period; and a digital analog converter generating the DAC output voltage in response to the DAC control signal.

Abstract translation: 模数转换器包括信号处理单元，响应于第一周期中的输入电压和DAC输出电压产生运算放大器输出电压，并且响应于反馈的运算放大器输出电压产生运算放大器输出电压，并且 DAC输出电压在第二个时期; 控制单元，通过将运算放大器输出电压与第一参考电压进行比较来产生DAC控制信号，以在第一周期内获得高位M位数据，并通过将运算放大器输出电压与第二和第 第三参考电压以在第二周期中获得低阶N位数据; 以及响应于DAC控制信号产生DAC输出电压的数字模拟转换器。

公开(公告)号：US20140191891A1

公开(公告)日：2014-07-10

申请号：US14209496

申请日：2014-03-13

Applicant: NORDIC SEMICONDUCTOR ASA

Inventor： Carsten Wulff ,  Ola Bruset ,  Werner Luzi

IPC: H03M3/00

CPC classification number: H03M3/39 ,  H03M3/38 ,  H03M3/43 ,  H03M3/456

Abstract: An integrated-circuit, continuous-time, sigma-delta analogue-to-digital converter has a single-ended analogue input, a converter reference input, and a ground connection. The converter has a resistor-capacitor integrator arranged to receive the single-ended analogue input. The integrator comprises a differential amplifier. The converter also has a clocked comparator connected to an output from the integrator, and circuitry arranged so that reference inputs to the amplifier and to the comparator can be maintained at a common voltage derived from the converter reference input.

Abstract translation: 集成电路，连续时间，Σ-Δ模数转换器具有单端模拟输入，转换器参考输入和接地连接。 该转换器具有一个电阻 - 电容积分器，用于接收单端模拟输入。 积分器包括差分放大器。 转换器还具有连接到积分器的输出的时钟比较器，并且被布置为使得放大器和比较器的参考输入可以保持在从转换器参考输入导出的公共电压的电路。

公开(公告)号：US20130147496A1

公开(公告)日：2013-06-13

申请号：US13762695

申请日：2013-02-08

Applicant: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.

Inventor： Stefan Moedl ,  Johann Hauer ,  Josef Sauerer

IPC: G01R27/26

CPC classification number: G01R27/2605 ,  G01D5/24 ,  H03M3/43 ,  H03M3/456

Abstract: A capacity measuring circuit includes a measuring voltage source configured to feed a sinusoidal voltage signal to a first terminal of a capacity to be measured so as to cause a temporal change in a charge stored on the capacity to be measured. The capacity measuring circuit additionally includes a delta-sigma modulator. The delta-sigma modulator is configured to receive a charge from a second terminal of the capacity to be measured and to provide a digital output signal which is dependent on a quantity of the charge received from the capacity to be measured. The capacity measuring circuit may be employed in a sensor system.

Abstract translation: 容量测量电路包括：测量电压源，被配置为将正弦电压信号馈送到要测量的电容的第一端子，以便引起存储在待测量电容上的电荷的时间变化。 容量测量电路还包括Δ-Σ调制器。 Δ-Σ调制器被配置为从待测量的容量的第二终端接收电荷，并且提供取决于从待测量的容量接收的电荷的量的数字输出信号。 容量测量电路可以用在传感器系统中。