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公开(公告)号：US20180205382A1
公开(公告)日：2018-07-19
申请号：US15408655
申请日：2017-01-18
Applicant: Integrated Device Technology, Inc.
Inventor： Hui Li , Teck-Chuan Ng , Stephen E. Aycock
Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal in a period determined by (i) an output clock signal and (ii) a second code. The second code may be variable. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal (i) in response to the third code and (ii) within an accuracy determined the second code.
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Patent Agency Ranking
公开(公告)号：US09954541B1
公开(公告)日：2018-04-24
申请号：US15084067
申请日：2016-03-29
Applicant: Integrated Device Technology, Inc.
Inventor： Pankaj Goyal , Stephen E. Aycock
CPC classification number: H03L7/183 , H03B5/12 , H03B5/32 , H03B5/326 , H03B5/366 , H03L7/099 , H03L7/23
Abstract: A frequency synthesizer comprising a first phase locked loop (PLL) circuit coupled to receive a reference frequency signal from a reference oscillator, the first PLL circuit comprising a first voltage controlled oscillator (VCO) having a bulk acoustic wave (BAW) resonator and a first fractional feedback divider circuit, the first PLL circuit outputting a first tuned frequency signal and a first plurality of integer divider circuits coupled to receive the first tuned frequency signal from the first PLL circuit and each of the first plurality of integer-only post-PLL divider circuits to provide one of a plurality of output frequency signals of the frequency synthesizer.
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3.发明授权公开(公告)号：US09581973B1
公开(公告)日：2017-02-28
申请号：US15083831
申请日：2016-03-29
Applicant: Integrated Device Technology, Inc.
Inventor： Pankaj Goyal , Jagdeep Bal , Stephen E. Aycock
CPC classification number: G04F5/04 , G04G3/02 , H03B5/32 , H03B5/364 , H03B2200/0082 , H03K5/15006
Abstract: An integrated circuit comprising, a resonator, a first clock circuit for generating a first clock signal having a first frequency in response to the resonator, a second clock circuit for generating a second clock signal having a second frequency in response to the resonator, wherein the second frequency of the second clock signal is determined by the programmable frequency divider and a clock mode control circuit coupled to the first clock circuit and the second clock circuit, the clock mode control circuit for gradually switching the resonator between the first oscillator circuit and the second oscillator circuit of the integrated circuit, using a shift register based state machine and utilizing the inertia of the resonator to smoothly transition between the two oscillators, to provide a dual mode clock output signal.
Abstract translation: 一种集成电路，包括谐振器，用于响应谐振器产生具有第一频率的第一时钟信号的第一时钟电路，用于响应谐振器产生具有第二频率的第二时钟信号的第二时钟电路，其中， 第二时钟信号的第二频率由可编程分频器和耦合到第一时钟电路和第二时钟电路的时钟模式控制电路确定，时钟模式控制电路用于在第一振荡器电路和第二时钟电路之间逐渐切换谐振器 振荡器电路，使用基于移位寄存器的状态机并利用谐振器的惯性在两个振荡器之间平滑地转换，以提供双模式时钟输出信号。
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公开(公告)号：US20190028105A1
公开(公告)日：2019-01-24
申请号：US16139340
申请日：2018-09-24
Applicant: Integrated Device Technology, Inc.
Inventor： Hui Li , Teck-Chuan Ng , Stephen E. Aycock
Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal during a period. The period may be determined by an output clock signal and a second code. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal in response to the third code. An accuracy of a frequency of the output clock signal may be determined by a current value of the second code.
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公开(公告)号：US10084457B2
公开(公告)日：2018-09-25
申请号：US15408655
申请日：2017-01-18
Applicant: Integrated Device Technology, Inc.
Inventor： Hui Li , Teck-Chuan Ng , Stephen E. Aycock
Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal in a period determined by (i) an output clock signal and (ii) a second code. The second code may be variable. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal (i) in response to the third code and (ii) within an accuracy determined the second code.
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公开(公告)号：US10483982B2
公开(公告)日：2019-11-19
申请号：US16139340
申请日：2018-09-24
Applicant: Integrated Device Technology, Inc.
Inventor： Hui Li , Teck-Chuan Ng , Stephen E. Aycock
Abstract: An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal during a period. The period may be determined by an output clock signal and a second code. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal in response to the third code. An accuracy of a frequency of the output clock signal may be determined by a current value of the second code.
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