公开(公告)号：US10374751B2

公开(公告)日：2019-08-06

申请号：US15154153

申请日：2016-05-13

Applicant: INTEL CORPORATION

Inventor： Adee O. Ran

IPC: H04L1/20 ,  H04L1/00 ,  H04L1/24

Abstract: Methods, apparatus, and systems for preventing false packet acceptance in high-speed links. Under one aspect, correctable symbol errors are detected, and determination is made to whether a symbol error rate or ratio (SER) exceeds an SER threshold. In response to detection of such a condition, the link is disconnected or temporarily paused. The value for the SER threshold is determined using a statistical analysis of various link parameters to meet desired performance levels, such as a mean time to false packet acceptance (MTTFPA) of >approximately 15 billion years while providing a mean time to disconnect of >100 years.

公开(公告)号：US10164912B2

公开(公告)日：2018-12-25

申请号：US15218681

申请日：2016-07-25

Applicant: Intel Corporation

Inventor： Adee O. Ran ,  David L. Chalupsky ,  Kevan A. Lillie ,  Richard I. Mellitz ,  Kent C. Lusted

IPC: H04L12/935

Abstract: Methods and apparatus for Ethernet auto-negotiation (AN) with parallel detect for 10G DAC or other non-auto-negotiated modes. AN base pages are transmitted from an Ethernet apparatus to advertise the ability to support at least one Institute of Electrical and Electronics Engineers (IEEE) 802.3 Ethernet specification supporting AN. A receiver and associated processing circuitry is configured to perform two detection modes in parallel, including a first detection mode that looks for a valid signal transmitted from an Ethernet link peer that does not support AN and a second detection mode looking for AN pages from an IEEE 802.3 Ethernet link peer that supports AN. If the link peer does not support AN, an Ethernet link is set up to use signaling in accordance with the Ethernet specification that does not support AN. If the link peer supports AN, an Ethernet link is set up using a corresponding IEEE 802.3 Ethernet link supporting AN. Supported non-AN Ethernet links include 10G DAC links.

公开(公告)号：US20180331907A1

公开(公告)日：2018-11-15

申请号：US16044122

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Kent C. Lusted ,  Adee O. Ran

IPC: H04L12/24

CPC classification number: H04L41/0886 ,  H04L49/3054 ,  H04L69/24

Abstract: Technologies for autonegotiation of communications operational modes over copper cable include a network port logic having a communication link coupled to a remote link partner. The network port logic may start an autonegotiation protocol upon reset, when the link is broken, or upon manual renegotiation. The network port logic transmits an autonegotiation page to the remote link partner that indicates single-lane communications ability over copper cable. The network port logic receives an autonegotiation page from the link partner indicating single-lane communications ability over copper cable. If the network port logic and link partner have a common single-lane communication ability, the link may be activated. The autonegotiation pages may be base pages or next pages. The single-lane communication ability may be indicated by one or more bits of the autonegotation pages. The link may be established at 1 gigabit or 10 gigabits per second. Other embodiments are described and claimed.

公开(公告)号：US09602401B2

公开(公告)日：2017-03-21

申请号：US14580737

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Adee O. Ran ,  Kent C. Lusted

IPC: H03M13/03 ,  H04L12/721 ,  H04L1/00 ,  H03M13/25

CPC classification number: H04L45/66 ,  H03M13/25 ,  H03M13/251 ,  H04L1/0041 ,  H04L1/0057 ,  H04L1/0083

Abstract: Technologies for high-speed data transmission include a network port logic having one or more communication lanes coupled to a forward error correction (FEC) sublayer and a physical coding sublayer (PCS). To transmit data, the PCS encodes the data to be transmitted into encoded data blocks using a 66 b/64 b line code and inserts alignment marker blocks after every 16,383 encoded data blocks. The FEC encodes the encoded data blocks into 80-block FEC codewords starting at a predefined offset from an alignment marker. Thus, each alignment marker is at one of five predefined offsets from the beginning of an FEC codeword. Each alignment marker may include a unique block type field usable with FEC encoding. The PCS may include one or more logical lanes, each operating at 25 Gb/s. Embodiments of the network port logic may include a single PCS lane or sixteen PCS lanes. Other embodiments are described and claimed.

公开(公告)号：US09568530B2

公开(公告)日：2017-02-14

申请号：US14527560

申请日：2014-10-29

Applicant: INTEL CORPORATION

Inventor： Ehud Udi Shoor ,  Dror Lazar ,  Adee O. Ran

IPC: G01R31/02 ,  G01M11/00 ,  H04B3/46 ,  H04B3/36

CPC classification number: G01R31/021 ,  G01M11/33 ,  H04B3/36 ,  H04B3/46

Abstract: Embodiments of the present disclosure provide configurations for testing arrangements for testing multi-lane active cables. In one embodiment, a testing arrangement may comprise a testing module comprising a pattern generator to be coupled with an active cable having a plurality of lanes to generate a test pattern to be transmitted over the active cable, wherein the test pattern is to be transmitted at least over two or more lanes of the active cable that are concatenated, and a processing unit to be coupled with the active cable to process a result of the transmission of the test pattern over the active cable. The arrangement may further include a plurality of testing cables to concatenate two or more of the lanes of the active cable, to enable the transmission of the test pattern over the concatenated lanes of the active cable. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供了用于测试多通道有源电缆的测试布置的配置。 在一个实施例中，测试装置可以包括测试模块，该测试模块包括与具有多个通道的有源电缆耦合的模式发生器，以产生将通过有源电缆传输的测试模式，其中测试模式将以 串联的有源电缆的至少两个或更多个通道，以及与有源电缆耦合以处理测试图案在有源电缆上传输的结果的处理单元。 该布置还可以包括多个测试电缆，以连接有源电缆的两条或更多条通道，以使测试图案能够在有源电缆的级联通道上传输。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09374202B2

公开(公告)日：2016-06-21

申请号：US13842320

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Adee O. Ran ,  Amir Mezer ,  Ophir Gazinski ,  Sanjay R. Ravi ,  David G. Ellis ,  Stephen J. Peters ,  Jeffrey M. Shuey

IPC: G06F11/00 ,  G01R19/00 ,  H04L1/00 ,  H04L1/20

CPC classification number: H04L1/203

Abstract: A sample voltage is received from a device at a first slicer element and a second slicer element. A decision by the first slicer element based on the sample voltage is identified and compared with a decision of the second slicer element based on the sample voltage. The decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element. Comparing the decisions can be the basis of a soft error ratio determined for a device.

Abstract translation: 从第一限幅元件和第二限幅元件的装置接收采样电压。 基于样本电压确定第一限幅元件的判定，并根据采样电压与第二限幅元件的判定进行比较。 第二限幅元件的决定是从采样电压与第二限幅元件的参考电压的比较产生的。 比较决策可以是为设备确定的软错误率的基础。

公开(公告)号：US09264270B2

公开(公告)日：2016-02-16

申请号：US13928648

申请日：2013-06-27

Applicant: INTEL CORPORATION

Inventor： Kent C. Lusted ,  Adee O. Ran

IPC: H03C1/52 ,  H04L27/04 ,  H04L25/49 ,  H04L25/03 ,  H04B17/10

CPC classification number: H04L25/4917 ,  H04B17/104 ,  H04L25/03343

Abstract: Methods, apparatus and systems for measuring signal transition times for a four-level pulse modulated amplitude (PAM4) transmitter. During a test procedure, a PAM4 transmitter is configured to repetitively transmit a PAM4 symbol test pattern, which is captured as a signal waveform. The test pattern includes at least one rising signal sequence having a PAM4 symbol pattern of at least three −1 PAM4 symbols followed by at least three +1 PAM4 symbols and at least one falling signal sequence having a PAM4 symbol pattern of at least three +1 PAM4 symbols followed by at least three −1 PAM4 symbols. A voltage modulation amplitude (VMA) level for each of a −1 and +1 PAM4 signal level is measured for at least one rising signal sequence and falling signal sequence to derive 20% and 80% VMA levels. A rise transition time is then determined by measuring the time interval between when a rising signal crosses the 20% and 80% VMA levels, and a fall transition time is determined by measuring the time interval between when a falling signal crosses the 80% and 20% VMA levels.

Abstract translation: 用于测量四电平脉冲调制幅度（PAM4）发射机的信号转换时间的方法，装置和系统。 在测试过程中，PAM4发射机被配置为重复地发送作为信号波形捕获的PAM4符号测试模式。 测试图案包括至少一个上升信号序列，其具有至少三个-1个PAM4符号的PAM4符号图案，其后跟至少三个+1PAM4符号，以及至少一个具有至少三个+1的PAM4符号图案的下降信号序列 PAM4符号后跟至少三个-1 PAM4符号。 对于至少一个上升信号序列和下降信号序列测量-1和+1个PAM4信号电平中的每一个的电压调制幅度（VMA）电平以得到20％和80％的VMA电平。 然后通过测量上升信号跨越20％和80％VMA电平之间的时间间隔来确定升高转变时间，并且通过测量下降信号跨越80％和20之间的时间间隔来确定下降转变时间 ％VMA级别。

公开(公告)号：US09344219B2

公开(公告)日：2016-05-17

申请号：US13926041

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Adee O. Ran

IPC: H03M13/00 ,  H04L1/00 ,  H04L1/20 ,  H04L1/24

CPC classification number: H04L1/0045 ,  H04L1/0038 ,  H04L1/0057 ,  H04L1/203 ,  H04L1/245

Abstract: Methods, apparatus, and systems for preventing false packet acceptance in high-speed links. Under one aspect, correctable symbol errors are detected, and determination is made to whether a symbol error rate or ratio (SER) exceeds an SER threshold. In response to detection of such a condition, the link is disconnected or temporarily paused. The value for the SER threshold is determined using a statistical analysis of various link parameters to meet desired performance levels, such as a mean time to false packet acceptance (MTTFPA) of >approximately 15 billion years while providing a mean time to disconnect of >100 years.

Abstract translation: 用于在高速链路中防止虚假包接收的方法，装置和系统。 在一个方面，检测到可校正的符号错误，并且确定符号错误率或比率（SER）是否超过SER阈值。 响应于这种情况的检测，链路断开或暂时暂停。 使用各种链路参数的统计分析来确定SER阈值的值，以满足期望的性能水平，例如>大约150亿年的假包接收的平均时间（MTTFPA），同时提供断开> 100的平均时间 年份。

公开(公告)号：US20150180592A1

公开(公告)日：2015-06-25

申请号：US14638507

申请日：2015-03-04

Applicant: Intel Corporation

Inventor： Adee O. Ran

IPC: H04B17/10 ,  H04L27/04

CPC classification number: H04B17/104 ,  G01R29/027 ,  G01R31/31709 ,  H04L1/205 ,  H04L1/24 ,  H04L1/248 ,  H04L27/04

Abstract: Methods and test equipment for measuring jitter in a Pulse Amplitude Modulated (PAM) transmitter. Under one procedure, a first two-level PAM signal test pattern is used to measure clock-related jitter separated into random and deterministic components, while a second two-level PAM signal test pattern is used to measure oven-odd jitter (EOJ). Under another procedure, A four-level PAM signal test pattern is used to measure jitter-induced noise using distortion analysis. Test equipment are also disclosed for implementing various aspects of the test methods.

Abstract translation: 用于测量脉冲幅度调制（PAM）发射机抖动的方法和测试设备。 在一个程序下，使用第一个两级PAM信号测试模式来测量分为随机和确定性分量的时钟相关抖动，而使用第二个两级PAM信号测试模式来测量烤箱奇数抖动（EOJ）。 在另一个程序中，使用四电平PAM信号测试模式来测量使用失真分析的抖动引起的噪声。 还公开了用于实施测试方法的各个方面的测试设备。

公开(公告)号：US20150003505A1

公开(公告)日：2015-01-01

申请号：US13928648

申请日：2013-06-27

Applicant: INTEL CORPORATION

Inventor： Kent C. Lusted ,  Adee O. Ran

IPC: H04B17/00 ,  H04L25/49

CPC classification number: H04L25/4917 ,  H04B17/104 ,  H04L25/03343

Abstract: Methods, apparatus and systems for measuring signal transition times for a four-level pulse modulated amplitude (PAM4) transmitter. During a test procedure, a PAM4 transmitter is configured to repetitively transmit a PAM4 symbol test pattern, which is captured as a signal waveform. The test pattern includes at least one rising signal sequence having a PAM4 symbol pattern of at least three −1 PAM4 symbols followed by at least three +1 PAM4 symbols and at least one falling signal sequence having a PAM4 symbol pattern of at least three +1 PAM4 symbols followed by at least three −1 PAM4 symbols. A voltage modulation amplitude (VMA) level for each of a −1 and +1 PAM4 signal level is measured for at least one rising signal sequence and falling signal sequence to derive 20% and 80% VMA levels. A rise transition time is then determined by measuring the time interval between when a rising signal crosses the 20% and 80% VMA levels, and a fall transition time is determined by measuring the time interval between when a falling signal crosses the 80% and 20% VMA levels.

Abstract translation: 用于测量四电平脉冲调制幅度（PAM4）发射机的信号转换时间的方法，装置和系统。 在测试过程中，PAM4发射机被配置为重复地发送作为信号波形捕获的PAM4符号测试模式。 测试图案包括至少一个上升信号序列，其具有至少三个-1个PAM4符号的PAM4符号图案，其后跟至少三个+1PAM4符号，以及至少一个具有至少三个+1的PAM4符号图案的下降信号序列 PAM4符号后跟至少三个-1 PAM4符号。 对于至少一个上升信号序列和下降信号序列测量-1和+1个PAM4信号电平中的每一个的电压调制幅度（VMA）电平以得到20％和80％的VMA电平。 然后通过测量上升信号跨越20％和80％VMA电平之间的时间间隔来确定升高转变时间，并且通过测量下降信号跨越80％和20之间的时间间隔来确定下降转变时间 ％VMA级别。