公开(公告)号：US09568530B2

公开(公告)日：2017-02-14

申请号：US14527560

申请日：2014-10-29

Applicant: INTEL CORPORATION

Inventor： Ehud Udi Shoor ,  Dror Lazar ,  Adee O. Ran

IPC: G01R31/02 ,  G01M11/00 ,  H04B3/46 ,  H04B3/36

CPC classification number: G01R31/021 ,  G01M11/33 ,  H04B3/36 ,  H04B3/46

Abstract: Embodiments of the present disclosure provide configurations for testing arrangements for testing multi-lane active cables. In one embodiment, a testing arrangement may comprise a testing module comprising a pattern generator to be coupled with an active cable having a plurality of lanes to generate a test pattern to be transmitted over the active cable, wherein the test pattern is to be transmitted at least over two or more lanes of the active cable that are concatenated, and a processing unit to be coupled with the active cable to process a result of the transmission of the test pattern over the active cable. The arrangement may further include a plurality of testing cables to concatenate two or more of the lanes of the active cable, to enable the transmission of the test pattern over the concatenated lanes of the active cable. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供了用于测试多通道有源电缆的测试布置的配置。 在一个实施例中，测试装置可以包括测试模块，该测试模块包括与具有多个通道的有源电缆耦合的模式发生器，以产生将通过有源电缆传输的测试模式，其中测试模式将以 串联的有源电缆的至少两个或更多个通道，以及与有源电缆耦合以处理测试图案在有源电缆上传输的结果的处理单元。 该布置还可以包括多个测试电缆，以连接有源电缆的两条或更多条通道，以使测试图案能够在有源电缆的级联通道上传输。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10129166B2

公开(公告)日：2018-11-13

申请号：US15465396

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Ehud Udi Shoor ,  Ari Sharon

IPC: H04L12/863 ,  H04L25/03 ,  H04L1/00 ,  G06F13/40 ,  G06F1/04 ,  H04B15/00

Abstract: Described is a low latency re-timer for systems supporting spread spectrum clocking. The re-timer comprises: a first clock frequency estimator to estimate a frequency of a receive clock (RX CLK) and to provide a first timestamp associated with a first clock that underwent spread spectrum; a second clock frequency estimator to estimate a frequency of a transmit clock (TX CLK) and to provide a second timestamp associated with a second clock that underwent spread spectrum; and a comparator to compare the first timestamp with the second timestamp.

公开(公告)号：US10673774B2

公开(公告)日：2020-06-02

申请号：US16140332

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Ehud Udi Shoor ,  Ari Sharon

IPC: H04L25/03 ,  H04L12/863 ,  H04L1/00 ,  G06F13/40 ,  G06F1/04 ,  H04B15/00 ,  H04L12/861

Abstract: Described is a low latency re-timer for systems supporting spread spectrum clocking. The re-timer comprises: a first clock frequency estimator to estimate a frequency of a receive clock (RX CLK) and to provide a first timestamp associated with a first clock that underwent spread spectrum; a second clock frequency estimator to estimate a frequency of a transmit clock (TX CLK) and to provide a second timestamp associated with a second clock that underwent spread spectrum; and a comparator to compare the first timestamp with the second timestamp.