公开(公告)号：US20230300063A1

公开(公告)日：2023-09-21

申请号：US18200342

申请日：2023-05-22

Applicant: Intel Corporation

Inventor： Helia A. NAEIMI ,  Amedeo SAPIO ,  John Andrew FINGERHUT ,  Yi LI ,  Yanfang LE

IPC: H04L45/16 ,  H04L69/22

CPC classification number: H04L45/16 ,  H04L69/22

Abstract: Examples described herein relate to a network interface device. The network interface device can include circuitry that is to: receive a first packet comprising a first packet header and a first packet payload; receive multiple subsequent packets comprising multiple packet headers for respective multiple subsequent packets; update at least one of the multiple packet headers; and construct egress packets. In some examples, the egress packets include respective one of the multiple packet headers and the first packet payload.

公开(公告)号：US20220109587A1

公开(公告)日：2022-04-07

申请号：US17552875

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Amedeo SAPIO ,  Daniel A. ALVAREZ ,  Anurag AGRAWAL

IPC: H04L12/18 ,  H04L1/16

Abstract: Examples described herein relate to a switch circuitry that includes circuitry to cause transmission, to multiple destinations, of copies of a packet received from a sender network interface device and circuitry to indicate acknowledgement of packet receipt, from the multiple destinations, to the sender network interface device based on receipt of acknowledgements of packet receipt from the multiple destinations. In some examples, the circuitry is to indicate acknowledgement of packet receipt, from the multiple destinations, to the sender network interface device with a packet index value.

公开(公告)号：US20230359582A1

公开(公告)日：2023-11-09

申请号：US18222946

申请日：2023-07-17

Applicant: Intel Corporation

Inventor： Vivek KASHYAP ,  Amedeo SAPIO

IPC: G06F15/173 ,  H04L47/193

CPC classification number: G06F15/17343 ,  H04L47/193

Abstract: Examples described herein relate to a switch comprising circuitry configured to for packet communications associated with a collective operation to train machine learning (ML) models: utilize a reliable transport protocol for communications from at least one worker node of the collective operation to a switch, wherein the utilize a reliable transport protocol for communications from at least one worker node of the collective operation to the switch comprises store packet receipt state for per-packet communications from the at least one worker node of the collective operation to the switch and utilize a non-reliable transport protocol by the switch to a device that is to perform aggregation of results, wherein the reliable transport protocol comprises a different protocol than that of the non-reliable transport protocol.

公开(公告)号：US20220245522A1

公开(公告)日：2022-08-04

申请号：US17723216

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Aswin RAMACHANDRAN ,  Amedeo SAPIO ,  Steven C. MILLER

IPC: G06N20/00

Abstract: Methods and apparatus for employing selective compression for addressing congestion control for Artificial Intelligence (AI) workloads. Multiple interconnected compute nodes are used for performing an AI workload in a distributed environment, such as training an AI model. Periodically, such as following an epoch for processing batches of training data in parallel, the compute nodes exchange Tensor data (e.g., local model gradients) with one another, which may lead to network/fabric congestion. Compute nodes and/or switches in the distributed environment are configured to detect current or projected network/fabric congestion and to selectively apply variable rate compression to packets containing the Tensor data to alleviate/avoid the congestion. Tensor data may be selectively applied at source compute nodes by computing a network pause time and comparing that time to a compression compute time. Switches may selectively compress packets to be forwarded to destination compute nodes based on buffer/queue fill levels and/or other network telemetry data.

公开(公告)号：US20220060418A1

公开(公告)日：2022-02-24

申请号：US17515222

申请日：2021-10-29

Applicant: Intel Corporation

Inventor： Yanfang LE ,  Daniel A. ALVAREZ ,  Amedeo SAPIO ,  John Andrew FINGERHUT

IPC: H04L12/741 ,  H04L12/721

Abstract: Examples described herein relate to a switch comprising: circuitry, when operational, to receive a packet comprising a header and a payload and in conjunction with performance of computation on the packet payload, forward the packet header, but not the payload, to a destination endpoint. In some examples, the destination endpoint of the packet is to perform management of reliable transport. In some examples, the circuitry includes programmable data plane circuitry comprising ingress pipeline or egress pipeline and one or more match action units (MAUs) to perform processing of the payload, wherein the programmable data plane circuitry is to perform computation on the packet payload.