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公开(公告)号：US20230300063A1
公开(公告)日：2023-09-21
申请号：US18200342
申请日：2023-05-22
Applicant: Intel Corporation
Inventor： Helia A. NAEIMI , Amedeo SAPIO , John Andrew FINGERHUT , Yi LI , Yanfang LE
Abstract: Examples described herein relate to a network interface device. The network interface device can include circuitry that is to: receive a first packet comprising a first packet header and a first packet payload; receive multiple subsequent packets comprising multiple packet headers for respective multiple subsequent packets; update at least one of the multiple packet headers; and construct egress packets. In some examples, the egress packets include respective one of the multiple packet headers and the first packet payload.
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公开(公告)号：US20230388281A1
公开(公告)日：2023-11-30
申请号：US18230588
申请日：2023-08-04
Applicant: Intel Corporation
Inventor： Helia A. NAEIMI , John Andrew FINGERHUT
IPC: H04L9/40
CPC classification number: H04L63/0485 , H04L63/166
Abstract: Examples described herein relate to an interface and circuitry coupled to the interface. The circuitry can provide an endpoint for a Transport Layer Security (TLS) over Remote Direct Memory Access (RDMA) connection with a first network interface device, provide an endpoint for a TLS over RDMA connection with a second network interface device, provide a transport layer endpoint for the packets received from the first network interface device, and provide a transport layer endpoint for the packets received from the second network interface device.
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公开(公告)号：US20240195749A1
公开(公告)日：2024-06-13
申请号：US18424376
申请日：2024-01-26
Applicant: Intel Corporation
Inventor： Anurag AGRAWAL , John Andrew FINGERHUT , Xiaoyan DING , Song ZHANG
IPC: H04L47/628 , H04L45/24 , H04L49/00
CPC classification number: H04L47/628 , H04L45/24 , H04L49/3063
Abstract: Examples described herein relate to a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine a path to transmit a packet based on relative network traffic transmitted via multiple paths. In some examples, determine a path to transmit a packet is based on Deficit Round Robin (DRR). In some examples, the programmable packet processing pipeline circuitry includes: a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes, a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and at least one child node is associated with the determined path.
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公开(公告)号：US20220060418A1
公开(公告)日：2022-02-24
申请号：US17515222
申请日：2021-10-29
Applicant: Intel Corporation
Inventor： Yanfang LE , Daniel A. ALVAREZ , Amedeo SAPIO , John Andrew FINGERHUT
IPC: H04L12/741 , H04L12/721
Abstract: Examples described herein relate to a switch comprising: circuitry, when operational, to receive a packet comprising a header and a payload and in conjunction with performance of computation on the packet payload, forward the packet header, but not the payload, to a destination endpoint. In some examples, the destination endpoint of the packet is to perform management of reliable transport. In some examples, the circuitry includes programmable data plane circuitry comprising ingress pipeline or egress pipeline and one or more match action units (MAUs) to perform processing of the payload, wherein the programmable data plane circuitry is to perform computation on the packet payload.
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公开(公告)号：US20240396844A1
公开(公告)日：2024-11-28
申请号：US18789463
申请日：2024-07-30
Applicant: Intel Corporation
Inventor： Shweta SHRIVASTAVA , Nupur JAIN , Arunkumar BALAKRISHNAN , John Andrew FINGERHUT , Neelakanta Venkatesh PETLA , Vishalakshi R
Abstract: Examples described herein relate to a network interface device comprising: an interface to a port; and circuitry to: perform parallel evaluation of multiple rules for a packet; drop the packet based at least in part on an indication by the parallel evaluation that communication with a target is not permitted; and permit communication of the packet based at least in part on a second indication by the parallel evaluation that communication with the target is permitted. In some examples, the parallel evaluation of multiple rules is to evaluate one or more of: a permitted sender Internet Protocol (IP) address range, a permitted destination IP address range, a permitted packet protocol, or a permitted egress port range.
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Patent Agency Ranking
公开(公告)号：US20230379154A1
公开(公告)日：2023-11-23
申请号：US18230594
申请日：2023-08-04
Applicant: Intel Corporation
Inventor： Helia A. NAEIMI , John Andrew FINGERHUT
CPC classification number: H04L9/32 , H04L63/166
Abstract: Examples described herein relate to an interface and circuitry coupled to the interface. The circuitry can provide an endpoint for a Datagram Transport Layer Security (DTLS) connection with a first network interface device, provide an endpoint for a second DTLS connection with a second network interface device, provide a transport layer endpoint for the packets received from the first network interface device, and provide a second transport layer endpoint for the packets received from the second network interface device.
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公开(公告)号：US20240080276A1
公开(公告)日：2024-03-07
申请号：US18503851
申请日：2023-11-07
Applicant: Intel Corporation
Inventor： Anurag AGRAWAL , John Andrew FINGERHUT , Xiaoyan DING , Song ZHANG
IPC: H04L47/628 , H04L45/24 , H04L49/00
CPC classification number: H04L47/628 , H04L45/24 , H04L49/3063
Abstract: Examples described herein relate to a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine a path to transmit a packet based on relative network traffic transmitted via multiple paths. In some examples, determine a path to transmit a packet is based on Deficit Round Robin (DRR). In some examples, the programmable packet processing pipeline circuitry includes: a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes, a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and at least one child node is associated with the determined path.
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公开(公告)号：US20230393814A1
公开(公告)日：2023-12-07
申请号：US18230605
申请日：2023-08-04
Applicant: Intel Corporation
Inventor： Helia A. NAEIMI , John Andrew FINGERHUT
IPC: G06F7/483
CPC classification number: G06F7/483
Abstract: Examples described herein relate to an interface and circuitry coupled to the interface, the circuitry configured to execute instructions that cause the circuitry to perform floating point (FP) operations based on floating point data received in different packets. The order of the floating point operations can be based on a reorder of the data received in the different packets and wherein the reorder of the data received in the different packets is different than the order in which the packets were received.
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公开(公告)号：US20230379309A1
公开(公告)日：2023-11-23
申请号：US18230600
申请日：2023-08-04
Applicant: Intel Corporation
Inventor： Helia A. NAEIMI , John Andrew FINGERHUT
CPC classification number: H04L63/0428 , H04L47/34
Abstract: Examples described herein relate to an interface and circuitry coupled to the interface. The circuitry can provide an endpoint for a PSP Security Protocol (PSP) connection to a first network interface device, provide an endpoint for a second PSP connection with a second network interface device, provide a transport layer endpoint for the packets received from the first network interface device, and provide a second transport layer endpoint for the packets received from the second network interface device.
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公开(公告)号：US20220109639A1
公开(公告)日：2022-04-07
申请号：US17550938
申请日：2021-12-14
Applicant: Intel Corporation
Inventor： Anurag AGRAWAL , John Andrew FINGERHUT , Xiaoyan DING , Song ZHANG
IPC: H04L47/628 , H04L45/24 , H04L49/00
Abstract: Examples described herein relate to a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine a path to transmit a packet based on relative network traffic transmitted via multiple paths. In some examples, determine a path to transmit a packet is based on Deficit Round Robin (DRR). In some examples, the programmable packet processing pipeline circuitry includes: a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes, a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and at least one child node is associated with the determined path.
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