公开(公告)号：US20190114114A1

公开(公告)日：2019-04-18

申请号：US16211108

申请日：2018-12-05

Applicant: Intel Corporation

Inventor： Sanjeev N. TRIKA ,  Steven C. MILLER

IPC: G06F3/06 ,  H03M13/15 ,  G06F11/10

Abstract: Techniques enable offloading operations to be performed closer to where the data is stored in systems with sharded and erasure-coded data, such as in data centers. In one example, a system includes a compute sled or compute node, which includes one or more processors. The system also includes a storage sled or storage node. The storage node includes one or more storage devices. The storage node stores at least one portion of data that is sharded and erasure-coded. Other portions of the data are stored on other storage nodes. The compute node sends a request to offload an operation to the storage node to access the sharded and erasure-coded data. The storage node then sends a request to offload the operation to one or more other storage nodes determined to store one or more codes of the data. The storage nodes perform the operation on the portions of locally stored data and provide the results to the next-level up node.

公开(公告)号：US20190042365A1

公开(公告)日：2019-02-07

申请号：US16142649

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Kimberly A. MALONE ,  Steven C. MILLER

IPC: G06F11/10 ,  H03M13/15

Abstract: Examples include techniques for performing read-optimized lazy erasure encoding of data streams. An embodiment includes receiving a request to write a stream of data, separating the stream into a first plurality of extents, storing a primary replica and one or more additional replicas of each extent of the separated stream to a plurality of data storage nodes, and updating a list of extents to be erasure encoded. The embodiment further includes when an erasure encoded stripe can be created, getting the data for each of the extents of the erasure encoded stripe, calculating parity extents for unencoded extents of the erasure encoded stripe, writing the parity extents to a second plurality of data storage nodes, and deleting the one or more additional replicas of the extents of the erasure encoded stripe from the first plurality of data storage nodes.

公开(公告)号：US20220245522A1

公开(公告)日：2022-08-04

申请号：US17723216

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Aswin RAMACHANDRAN ,  Amedeo SAPIO ,  Steven C. MILLER

IPC: G06N20/00

Abstract: Methods and apparatus for employing selective compression for addressing congestion control for Artificial Intelligence (AI) workloads. Multiple interconnected compute nodes are used for performing an AI workload in a distributed environment, such as training an AI model. Periodically, such as following an epoch for processing batches of training data in parallel, the compute nodes exchange Tensor data (e.g., local model gradients) with one another, which may lead to network/fabric congestion. Compute nodes and/or switches in the distributed environment are configured to detect current or projected network/fabric congestion and to selectively apply variable rate compression to packets containing the Tensor data to alleviate/avoid the congestion. Tensor data may be selectively applied at source compute nodes by computing a network pause time and comparing that time to a compression compute time. Switches may selectively compress packets to be forwarded to destination compute nodes based on buffer/queue fill levels and/or other network telemetry data.

公开(公告)号：US20230180421A1

公开(公告)日：2023-06-08

申请号：US17540936

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Carl D. WILLIAMS ,  Steven C. MILLER

IPC: H05K7/14

CPC classification number: H05K7/1492 ,  H05K7/1491

Abstract: An apparatus is described. The apparatus includes a rack shelf back interface. The rack shelf back interface has first and second flanges to mount to a rack’s rear facing rack mounts. The rack shelf back interface has a power connector610 on an inside of a back face of the rack shelf interface, the power connector to mate with a corresponding power connector on an electronic system that is to be installed in the rack shelf. The rack shelf back interface has an alignment feature on the inside of the back face of the rack shelf interface to ensure that the power connector properly mates with the corresponding power connector.

公开(公告)号：US20220173015A1

公开(公告)日：2022-06-02

申请号：US17676105

申请日：2022-02-18

Applicant: Intel Corporation

Inventor： Prabhakar SUBRAHMANYAM ,  Jack D. MUMBO ,  Carl D. WILLIAMS ,  Steven C. MILLER

IPC: H01L23/473 ,  H01L23/40 ,  H05K7/20

Abstract: An apparatus is described. The apparatus includes a cold plate. The cold plate includes an input port to receive cooled fluid. The cold plate includes an ingress manifold to feed the cooled fluid to different regions, where, each of the different regions are to be located above its own respective semiconductor chip package. The cold plate includes an egress manifold to collect warmed fluid from the different regions. The cold plate includes an output port to emit the warmed fluid from the cold plate.