公开(公告)号：US10854249B2

公开(公告)日：2020-12-01

申请号：US16914310

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Navindra Navaratnam ,  Nasser A. Kurd ,  Bee Min Teng ,  Raymond Chong ,  Nasirul I. Chowdhury ,  Ali M. El-Husseini

IPC: G11C29/50 ,  G11C7/22 ,  H03K5/135 ,  G11C7/10 ,  H01L25/18 ,  H03K5/00 ,  H01L23/00

Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.

公开(公告)号：US20200143853A1

公开(公告)日：2020-05-07

申请号：US16178346

申请日：2018-11-01

Applicant: Intel Corporation

Inventor： Navindra Navaratnam ,  Nasser A. Kurd ,  Bee Min Teng ,  Raymond Chong ,  Nasirul I. Chowdhury ,  Ali M. El-Husseini

IPC: G11C7/22 ,  H03K5/135 ,  G11C7/10 ,  H01L25/18

Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.

公开(公告)号：US20210082481A1

公开(公告)日：2021-03-18

申请号：US17107704

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： Navindra Navaratnam ,  Nasser A. Kurd ,  Bee Min Teng ,  Raymond Chong ,  Nasirul I. Chowdhury ,  Ali M. El-Husseini

IPC: G11C7/22 ,  H03K5/135 ,  G11C7/10 ,  H01L25/18

Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.

公开(公告)号：US20200327914A1

公开(公告)日：2020-10-15

申请号：US16914310

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Navindra Navaratnam ,  Nasser A. Kurd ,  Bee Min Teng ,  Raymond Chong ,  Nasirul I. Chowdhury ,  Ali M. El-Husseini

IPC: G11C7/22 ,  H03K5/135 ,  G11C7/10 ,  H01L25/18

Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.

公开(公告)号：US11183226B2

公开(公告)日：2021-11-23

申请号：US17107704

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： Navindra Navaratnam ,  Nasser A. Kurd ,  Bee Min Teng ,  Raymond Chong ,  Nasirul I. Chowdhury ,  Ali M. El-Husseini

IPC: G11C29/50 ,  G11C7/22 ,  H03K5/135 ,  G11C7/10 ,  H01L25/18 ,  H03K5/00 ,  H01L23/00

Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.

公开(公告)号：US11037607B2

公开(公告)日：2021-06-15

申请号：US16220523

申请日：2018-12-14

Applicant: Intel Corporation

Inventor： Raymond Chong ,  Bee Min Teng ,  Christopher Mozak

IPC: G01R19/00 ,  G11C7/00 ,  G11C7/06 ,  H03K3/037 ,  G11C7/10 ,  H04L7/00 ,  G11C11/16 ,  H04B1/16 ,  G11C7/08

Abstract: Described is an apparatus to widen or improve a common mode range of a strong arm latch (SAL). In some embodiments, the SAL comprises a master-slave architecture with a common latch. The apparatus includes: a sampler to sample an input with a first clock, and to provide a sampled output on a node. The SAL is to receive the sampled output on the node, and to sample the sampled output according to a second clock. The apparatus comprises a digital-to-analog converter (DAC) coupled to the node, wherein the DAC is to adjust a common mode of the sampled output according to a digital control to the DAC.

公开(公告)号：US10706900B2

公开(公告)日：2020-07-07

申请号：US16178346

申请日：2018-11-01

Applicant: Intel Corporation

Inventor： Navindra Navaratnam ,  Nasser A. Kurd ,  Bee Min Teng ,  Raymond Chong ,  Nasirul I. Chowdhury ,  Ali M. El-Husseini

IPC: G11C29/50 ,  G11C7/22 ,  H03K5/135 ,  G11C7/10 ,  H01L25/18 ,  H03K5/00 ,  H01L23/00

Abstract: An apparatus is provided for mitigating uncertainties in process, voltage, random, and systematic variations between first and second dies. The first die comprises a clock compensator to adjust one or more signal characteristics of an input clock, and to provide first and second clocks; a data transmitter to sample data with a version of the first clock and to transmit the sampled data to a data receiver of the second die, wherein the data receiver is to receive the sampled data and generate a received data; and a clock transmitter to transmit the second clock to a clock receiver of the second die, wherein the clock receiver is to generate a third clock, wherein a phase of the third clock is adjusted to generate a fourth clock, wherein a delayed version of the fourth clock is received by a sampler coupled to the data receiver to sample the received data.