公开(公告)号：US20230369444A1

公开(公告)日：2023-11-16

申请号：US17742656

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Albert B. Chen ,  Mark Armstrong ,  Afrin Sultana ,  Van H. Le ,  Travis W. Lajoie ,  Shailesh Kumar Madisetti ,  Timothy Jen ,  Cheng Tan ,  Moshe Dolejsi ,  Vishak Venkatraman ,  Christopher Ryder ,  Deepyanti Taneja

IPC: H01L29/51 ,  H01L27/108 ,  H01L29/786 ,  H01L29/417 ,  H01L23/522

CPC classification number: H01L29/513 ,  H01L27/10805 ,  H01L29/7869 ,  H01L29/41733 ,  H01L23/5226

Abstract: Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.