公开(公告)号：US20230371233A1

公开(公告)日：2023-11-16

申请号：US17742628

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Travis W. Lajoie ,  Forough Mahmoudabadi ,  Shailesh Kumar Madisetti ,  Van H. Le ,  Timothy Jen ,  Cheng Tan ,  Jisoo Kim ,  Miriam R. Reshotko ,  Vishak Venkatraman ,  Eva Vo ,  Yue Zhong ,  Yu-Che Chiu ,  Moshe Dolejsi ,  Lorenzo Ferrari ,  Akash Kannegulla ,  Deepyanti Taneja ,  Mark Armstrong ,  Kamal H. Baloch ,  Afrin Sultana ,  Albert B. Chen ,  Vamsi Evani ,  Yang Yang ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/786 ,  H01L29/94

CPC classification number: H01L27/10805 ,  H01L23/5283 ,  H01L29/78696 ,  H01L29/94

Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.

公开(公告)号：US20230369506A1

公开(公告)日：2023-11-16

申请号：US17742649

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Miriam R. Reshotko ,  Van H. Le ,  Travis W. Lajoie ,  Mark Armstrong ,  Cheng Tan ,  Timothy Jen ,  Moshe Dolejsi ,  Deepyanti Taneja

IPC: H01L29/786 ,  H01L23/528 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L29/78645 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/10814

Abstract: Techniques are provided herein for forming thin film transistor structures having a laterally recessed gate electrode. The gate electrode may be recessed such that it does not extend under one or both conductive contacts of the transistor. Recessing the lateral dimensions of the gate electrode can reduce gate leakage current and parasitic capacitance. According to an example, a given memory structure generally includes memory cells, with each memory cell having an access device and a storage device. According to some such embodiments, the memory cells are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory cell arrays are formed within the interconnect region. Any of the given TFT structures may include a gate electrode that is laterally recessed such that one or more of the contacts are not directly over the gate electrode.

公开(公告)号：US20230369444A1

公开(公告)日：2023-11-16

申请号：US17742656

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Albert B. Chen ,  Mark Armstrong ,  Afrin Sultana ,  Van H. Le ,  Travis W. Lajoie ,  Shailesh Kumar Madisetti ,  Timothy Jen ,  Cheng Tan ,  Moshe Dolejsi ,  Vishak Venkatraman ,  Christopher Ryder ,  Deepyanti Taneja

IPC: H01L29/51 ,  H01L27/108 ,  H01L29/786 ,  H01L29/417 ,  H01L23/522

CPC classification number: H01L29/513 ,  H01L27/10805 ,  H01L29/7869 ,  H01L29/41733 ,  H01L23/5226

Abstract: Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.

公开(公告)号：US20230369426A1

公开(公告)日：2023-11-16

申请号：US17742636

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Travis W. Lajoie ,  Van H. Le ,  Timothy Jen ,  Kamal H. Baloch ,  Mark Armstrong ,  Albert B. Chen ,  Moshe Dolejsi ,  Shailesh Kumar Madisetti ,  Afrin Sultana ,  Deepyanti Taneja ,  Vishak Venkatraman

IPC: H01L29/417 ,  H01L29/786 ,  H01L23/528 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L29/41733 ,  H01L29/78618 ,  H01L29/7869 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/10805

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.

公开(公告)号：US20230317615A1

公开(公告)日：2023-10-05

申请号：US17708051

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Deepyanti Taneja ,  Travis W. Lajoie ,  Abhishek Anil Sharma ,  Gregory J. George ,  Tarannum Tiasha ,  Huiying Liu ,  Yue Liu ,  Moshe Dolejsi ,  Vinaykumar V. Hadagali ,  Shardul Wadekar ,  Vladimir Nikitin ,  Albert B. Chen ,  Daniel J. Schinke ,  James O'Donnell

IPC: H01L23/532 ,  H01L27/12

CPC classification number: H01L23/53295 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1255 ,  H01L23/5226

Abstract: An integrated circuit includes a first layer, and a second layer above the first layer. A third layer is between a first section of the first layer and a first section of the second layer. A fourth layer is laterally adjacent to the third layer, the fourth layer between a second section of the first layer and a second section of the second layer. In an example, a first dielectric material of the third layer is different (e.g., one or both of compositionally different and structurally different) from a second dielectric material of the fourth layer. In an example, the third and fourth layers are etch stop layers. In some cases, the third and fourth layers are coplanar with each other with respect to their top surfaces, or their bottom surfaces, or both their top and bottom surfaces.

公开(公告)号：US20230307291A1

公开(公告)日：2023-09-28

申请号：US17656366

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Moshe Dolejsi ,  Harish Ganapathy ,  Travis W. Lajoie ,  Deepyanti Taneja ,  Huiying Liu ,  Cheng Tan ,  Timothy Jen ,  Van H. Le ,  Abhishek A. Sharma

IPC: H01L21/768 ,  H01L27/108 ,  H01L23/522

CPC classification number: H01L21/76829 ,  H01L21/76859 ,  H01L23/5226 ,  H01L27/10852

Abstract: An integrated circuit includes a first layer comprising dielectric material. One or both of an interconnect feature and a device are within the dielectric material of the first layer. The integrated circuit further includes a second layer above the first layer, where the second layer includes dielectric material. A third layer is between the first layer and the second layer. In an example, the third layer can be, for example, an etch stop layer or a liner layer or barrier layer. In an example, an impurity is within the first layer and the third layer. In an example, the impurity has a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer.

公开(公告)号：US20230290726A1

公开(公告)日：2023-09-14

申请号：US17692346

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Moshe Dolejsi ,  Travis W. Lajoie ,  Abhishek Anil Sharma

IPC: H01L23/528 ,  H01L21/768 ,  H01L27/108

CPC classification number: H01L23/528 ,  H01L21/76897 ,  H01L21/76834 ,  H01L27/10805

Abstract: An integrated circuit includes a first conductive structure, a second conductive structure, and a first spacer and a second spacer each comprising a first dielectric material. The integrated circuit further includes a layer comprising a second dielectric material that is compositionally different from the first dielectric material. The integrated circuit further includes a first interconnect feature above and at least partially landed on the first conductive structure. In an example, the first interconnect feature is laterally between the first spacer and the second spacer. The integrated circuit further includes a second interconnect feature above and at least partially landed on the second conductive structure. In an example, the second interconnect feature is laterally between the second spacer and the layer comprising the second dielectric material.

公开(公告)号：US20230290722A1

公开(公告)日：2023-09-14

申请号：US17692350

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Juan Alzate Vinasco ,  Abhishek Anil Sharma ,  Van H. Le ,  Moshe Dolejsi ,  Yu-Wen Huang ,  Kimberly Pierce ,  Jared Stoeger ,  Shem Ogadhoh

IPC: H01L23/522 ,  H01L27/108 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L27/10814 ,  H01L27/10855 ,  H01L23/53266 ,  H01L23/53238 ,  H01L23/53223 ,  H01L23/5283

Abstract: An integrated circuit (IC) includes a first memory cell and a second memory cell. The first memory cell includes (i) a first transistor and (ii) a first capacitor coupled to the first transistor, where an upper electrode of the first capacitor is coupled to a first conductive structure. The second memory cell is above the first memory cell. The second memory cell includes (i) a second transistor and (ii) a second capacitor coupled to the second transistor. An upper electrode of the second capacitor is coupled to a second conductive structure. In an example, an interconnect feature includes a continuous and monolithic body of conductive material. In an example, the continuous and monolithic body extends through the second conductive structure, and further extends through the first conductive structure. In an example, the first and second memory cells are dynamic random access memory (DRAM) memory cells.