公开(公告)号：US20230369509A1

公开(公告)日：2023-11-16

申请号：US17742638

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Jisoo Kim ,  Xiaoye Qin ,  Timothy Jen ,  Harish Ganapathy ,  Van H. Le ,  Huiying Liu ,  Prem Chanani ,  Cheng Tan ,  Shailesh Kumar Madisetti ,  Abhishek Anil Sharma ,  Brian Wadsworth ,  Vishak Venkatraman ,  Andre Baran

IPC: H01L29/786 ,  H01L23/528 ,  H01L27/108

CPC classification number: H01L29/7869 ,  H01L23/5283 ,  H01L27/10814

Abstract: Techniques are provided herein for forming thin film transistor (TFT) structures having one or more doped contact regions. The addition of certain dopants can be used to increase conductivity and provide higher thermal stability in the contact regions of the TFT. Memory structures having TFT structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the TFT structures within the memory structures may include one or more contacts that are doped with additional elements. The doping profile of the contacts can be tuned to optimize performance, stability, and reliability of the TFT structure. Furthermore, additional doping may be performed within the area beneath the contacts and extending into the semiconductor region.

公开(公告)号：US20230369426A1

公开(公告)日：2023-11-16

申请号：US17742636

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Travis W. Lajoie ,  Van H. Le ,  Timothy Jen ,  Kamal H. Baloch ,  Mark Armstrong ,  Albert B. Chen ,  Moshe Dolejsi ,  Shailesh Kumar Madisetti ,  Afrin Sultana ,  Deepyanti Taneja ,  Vishak Venkatraman

IPC: H01L29/417 ,  H01L29/786 ,  H01L23/528 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L29/41733 ,  H01L29/78618 ,  H01L29/7869 ,  H01L23/5283 ,  H01L23/5226 ,  H01L27/10805

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer contact structures. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, a semiconductor region on the gate dielectric, and a conductive contact that contacts at least a portion of the semiconductor region. In some other cases, the conductive contact comprises a multilayer structure having at least a first material layer on the at least a portion of the semiconductor region, at least a second material layer on the first material layer, and a conductive fill material over the first and second material layers. In some other cases, the conductive contact comprises a multilayer structure having (1) a graded material layer on the at least a portion of the semiconductor region and (2) a conductive fill material over the graded material layer, wherein the graded material layer comprises a concentration gradient of a given element.

公开(公告)号：US20230371233A1

公开(公告)日：2023-11-16

申请号：US17742628

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Travis W. Lajoie ,  Forough Mahmoudabadi ,  Shailesh Kumar Madisetti ,  Van H. Le ,  Timothy Jen ,  Cheng Tan ,  Jisoo Kim ,  Miriam R. Reshotko ,  Vishak Venkatraman ,  Eva Vo ,  Yue Zhong ,  Yu-Che Chiu ,  Moshe Dolejsi ,  Lorenzo Ferrari ,  Akash Kannegulla ,  Deepyanti Taneja ,  Mark Armstrong ,  Kamal H. Baloch ,  Afrin Sultana ,  Albert B. Chen ,  Vamsi Evani ,  Yang Yang ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/786 ,  H01L29/94

CPC classification number: H01L27/10805 ,  H01L23/5283 ,  H01L29/78696 ,  H01L29/94

Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.

公开(公告)号：US20220359758A1

公开(公告)日：2022-11-10

申请号：US17308853

申请日：2021-05-05

Applicant: Intel Corporation

Inventor： Shailesh Kumar Madisetti ,  Chieh-Jen Ku ,  Wen-Chiang Hong ,  Pei-Hua Wang ,  Cheng Tan ,  Harish Ganapathy ,  Bernhard Sell ,  Lin-Yung Wang

IPC: H01L29/786 ,  H01L29/66

Abstract: Transistors with metal oxide channel material and a multi-composition gate dielectric. A surface of a metal oxide gate dielectric may be nitrided before deposition of a metal oxide channel material, for example to reduce gate capacitance of a TFT. Breakdown voltage and/or drive current of a TFT can be increased through the introduction of an additional metal oxide and/or nitride between the gate electrode and a metal oxide gate dielectric. The introduction of an intervening layer between two layers of a metal oxide gate dielectric can also increase breakdown voltage and/or drive current of a TFT.

公开(公告)号：US20230369508A1

公开(公告)日：2023-11-16

申请号：US17742644

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Timothy Jen ,  Prem Chanani ,  Cheng Tan ,  Brian Wadsworth ,  Andre Baran ,  James Pellegren ,  Christopher J. Wiegand ,  Van H. Le ,  Abhishek Anil Sharma ,  Shailesh Kumar Madisetti ,  Xiaojun Weng

IPC: H01L29/786 ,  H01L23/528 ,  H01L27/108

CPC classification number: H01L29/78687 ,  H01L23/5283 ,  H01L29/7869 ,  H01L27/10814

Abstract: Techniques for forming thin film transistors (TFTs) having multilayer and/or concentration gradient semiconductor regions. An example integrated circuit includes a gate electrode, a gate dielectric on the gate electrode, and a semiconductor region on the gate dielectric. In some cases, the semiconductor region includes a plurality of compositionally different material layers, at least two layers of the different material layers each being a semiconductor layer. In some other cases, the semiconductor region includes a single layer having a material concentration gradient extending from a bottom surface of the single layer (adjacent to the gate dielectric) to a top surface of the single layer. The integrated circuit further includes first and second conductive contacts that each contact a respective portion of the semiconductor region. One example application of the techniques is with respect to forming backend (within the interconnect region) memory structures configured with multilayer and/or concentration gradient TFTs.

公开(公告)号：US20230369444A1

公开(公告)日：2023-11-16

申请号：US17742656

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Abhishek Anil Sharma ,  Albert B. Chen ,  Mark Armstrong ,  Afrin Sultana ,  Van H. Le ,  Travis W. Lajoie ,  Shailesh Kumar Madisetti ,  Timothy Jen ,  Cheng Tan ,  Moshe Dolejsi ,  Vishak Venkatraman ,  Christopher Ryder ,  Deepyanti Taneja

IPC: H01L29/51 ,  H01L27/108 ,  H01L29/786 ,  H01L29/417 ,  H01L23/522

CPC classification number: H01L29/513 ,  H01L27/10805 ,  H01L29/7869 ,  H01L29/41733 ,  H01L23/5226

Abstract: Techniques are provided herein for forming thin film transistor structures having a multilayer and/or concentration gradient gate dielectric. Such a gate dielectric can be used, to tune the performance and/or reliability of the transistor. According to some such embodiments, memory structures having thin film transistor (TFT) structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the given TFT structures may include a multilayer and/or graded gate dielectric that includes at least two or more different dielectric layers and/or a material concentration gradient through a thickness of the gate dielectric.

公开(公告)号：US20230369340A1

公开(公告)日：2023-11-16

申请号：US17742651

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Van H. Le ,  Timothy Jen ,  Vishak Venkatraman ,  Shailesh Kumar Madisetti ,  Cheng Tan ,  Harish Ganapathy ,  James Pellegren ,  Kamal H. Baloch ,  Abhishek Anil Sharma

IPC: H01L27/12 ,  H01L29/786 ,  H01L23/528 ,  H01L27/108

CPC classification number: H01L27/1225 ,  H01L29/7869 ,  H01L23/5283 ,  H01L27/1255 ,  H01L27/10805

Abstract: Techniques are provided herein for forming thin film transistor structures having co-doped semiconductor regions. The addition of insulating dopants can be used to improve the performance, stability, and reliability of the TFT. A given TFT structure within an array of similar TFT structures formed in an interconnect region may include a semiconductor region that is co-doped with one or more additional elements. The doping profile can be tuned to optimize performance, stability, and reliability of the TFT structure. In some embodiments, the doping profile causes an overall reduction in the conductivity of the semiconductor region, leading to a higher threshold voltage. Designing access devices (in, for example, a DRAM architecture) with higher threshold voltages can be beneficial for improving reliability of the memory cell.

公开(公告)号：US20230080212A1

公开(公告)日：2023-03-16

申请号：US17476165

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Christopher Connor ,  James O'Donnell ,  Shailesh Kumar Madisetti

IPC: H01L29/786 ,  H01L29/66

Abstract: A thin film transistor (TFT) structure. In an example, the TFT includes a gate electrode, a first layer comprising an oxide semiconductor material, and a second layer between the first layer and the gate electrode. The second layer is crystalline and is in contact with the first layer, and includes zirconium and oxygen. The TFT includes a first contact coupled to the first layer at a first location, and a second contact coupled to the first layer at a second location. In some cases, the second layer further includes hafnium. In some cases, the TFT includes a third layer between of the gate electrode and the second layer, the third layer comprising a metal and oxygen. The gate electrode may also include the metal. In some cases, hydrogen is present at an interface between the gate electrode and the second layer.